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| OMAP5910 Dual-Core Processor Data Manual Literature Number: SPRS197D August 2002 - Revised August 2004 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless Revision History REVISION HISTORY This data sheet revision history highlights the technical changes made to the SPRS197C device-specific data sheet to make it an SPRS197D revision. Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date and includes the following changes. PAGE(S) NO. All ADDITIONS/CHANGES/DELETIONS Removed all references to MMC/SD SPI mode that is no longer supported. In Table 2-1: Added footnote for GZG pin V12; "See Section 5.6.1 and Section 5.6.2 for special VSS considerations with oscillator circuits." Changed GZG pin P9 from "USB0.DP" to "USB.DP" In Table 2-2: Added footnote for GDY pin F6; "See Section 5.6.1 and Section 5.6.2 for special VSS considerations with oscillator circuits." Changed GDY pin P5 from "USB0.DP" to "USB.DP" In Table 2-4: Added A11, A13, H9, and G9 to list o f VSS Pins Changed U21 to N16 in the GDY column Changed USB1.TXEN pin in the GDY column from T6 to P14 Changed LCD.PCLK and LCD.P[15:0] description from "LCD panels" to "LCD panel" Changed SDRAM.CLK description to include "SDRAM.CLK can also be configured as an input to monitor skew control." Changed STAT_VAL/WKUP description to remove "STAT_VAL/WKUP may be configured via software to function as an external wake-up signal to the OMAP5910 device to request chip wake-up during sleep modes." Changed last bullet in Section 3.1 from: LCD controller supporting monochrome panels or STN and TFT color panels to: LCD controller supporting monochrome panels (STN) and color panels (STN or TFT) In Section 3.3.4, changed the last sentence in the first paragraph from: Accessing registers with the incorrect access width may result in unexpected results including a TI Peripheral Bus (TIPB) bus error and associated TIPB interrupt. to: Accessing registers with the incorrect access width may cause unexpected results including a TI Peripheral Bus (TIPB) bus error and associated TIPB interrupt. Combined bullets: 18 - 21 22 - 24 34 - 46 48 54 64 * * * Selectable UART/autobauding modes (autobauding on UART1 and UART2) Auto bauding between 1200bits/s and 115.2K bits/s Selectable UART/autobauding modes (autobauding on UART1 and UART2) with autobauding between 1200 bits/s and 115.2K bits/s To read as follows: 66 Revised Section 3.11 to removed bulleted list and replace with the following: "The EMIFF Interface provides access to 16-bit-wide access to standard SDRAM memories and the IMIF provides access to the 192K bytes of on-chip SRAM." August 2002 - Revised August 2004 SPRS197D 3 Revision History PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS In Section 3.13, removed the following bulleted items: 68 * * * * Quantization /Dequantization (useful for JPEG, MPEG, H.26x Encoding/Decoding) Flexible 1D/2D Wavelet Processing (useful for JPEG2000, MPEG4, and other compression standards) Boundary and Perimeter Computation (useful for Machine Vision applications) Image Threshold and Histogram Computations (useful for various Image Analysis applications) 72 120 Revised Table 3-17 to change access width from 32 bit to 16 bit. Changed MPU_READ_TIM_WD address to FFFE:C804 and changed MPU_TIMER_MODE_WD address to FFFE:C808. Revised Section 4.1 and added Figure 4-1, OMAP Device Nomenclature Changed Section 5.6.2, first paragraph, third line from "If the internal oscillator is not used (configured in software), an external clock source must be applied to the OSC1_IN pin and the OSC1_OUT pin must be left unconnected." to "If the internal oscillator is not used (configured in software using FUNC_MUX_CTRL_B register), an external clock source must be applied to the OSC1_IN pin and the OSC1_OUT pin must be left unconnected." Revised Table 5-10 Revised Table 5-11 Changed footnote of Table 5-14 from: "P = 1/(Base frequency) for McBSP1 and 3, or 1/(AMPER_CK clock frequency) in nanoseconds (ns) for McBSP 2.Base frequency is 12 or 13MHz". to: "Regardless of whether MCBSP.CLKS is internally or externally clocked, P = 1/(DSPXOR_CK) for McBSP1 and McBSP3, and P = 1/(AMPER_CK) for McBSP2. See the OMAP5910 Dual-Core Processor Clock Generation and System Reset Management Reference Guide (literature number SPRU678) for additional details." 126 130 131 141 - 142 4 SPRS197D August 2002 - Revised August 2004 Contents Contents Section 1 2 OMAP5910 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 TMS320C55x DSP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 TI-Enhanced TI925T RISC Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Terminal Characteristics and Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Functional Block Diagram Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 MPU Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 MPU Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 MPU Subsystem Registers Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 DSP Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 DSP Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 On-Chip Dual-Access RAM (DARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 On-Chip Single-Access RAM (SARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4 DSP I/O Space Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 DSP External Memory (Managed by MMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 MPU and DSP Private Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 32k Timer (MPU only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.4 Interrupt Handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.5 LCD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 MPU Public Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 USB Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 USB Function Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 Multichannel Buffered Serial Port (McBSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.4 I2C Master/Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.5 MICROWIRE Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.6 Multimedia Card/Secure Digital (MMC/SD) Interface . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.7 HDQ/1-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.8 Camera Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.9 MPUIO/Keyboard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.10 Pulse-Width Light (PWL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.11 Pulse-Width Tone (PWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.12 LED Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.13 Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.14 Frame Adjustment Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 DSP Public Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 Multichannel Buffered Serial Port (McBSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 Multichannel Serial Interface (MCSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 15 16 16 16 17 18 24 34 47 48 50 50 51 52 52 53 53 54 55 57 57 57 57 57 57 58 58 59 59 60 60 60 61 61 61 61 61 62 62 62 62 62 63 3 August 2002 - Revised August 2004 SPRS197D 5 Contents Section 3.8 Shared Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 General-Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.3 Mailbox Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Traffic Controller (Memory Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interprocessor Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.1 MPU/DSP Mailbox Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.2 MPU Interface (MPUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.3 MPU/DSP Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Hardware Accelerators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.1 DCT/iDCT Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.2 Motion Estimation Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.3 Pixel Interpolation Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Connection Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14.1 Core and I/O Voltage Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14.2 Core Voltage Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15.1 MPU Private Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15.2 MPU Public Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15.3 MPU Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.1 DSP Private Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.2 DSP Public Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.3 DSP Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.4 MPU/DSP Shared Peripheral Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU System DMA Request Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP DMA Event Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 63 63 64 64 65 66 66 67 67 67 68 68 68 68 68 68 68 70 71 72 79 88 95 95 101 106 108 113 117 118 119 120 121 121 122 123 124 124 125 125 126 127 128 128 129 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4 Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Device and Development Tool Support Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 32-kHz Oscillator and Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 Base Oscillator (12 MHz or 13 MHz) and Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.3 Internal Clock Speed Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 OMAP5910 Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2 OMAP5910 MPU Core Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 SPRS197D August 2002 - Revised August 2004 Contents Section 5.8 External Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.1 EMIFS/Flash Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.2 EMIFF/SDRAM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Buffered Serial Port (McBSP) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.1 McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.2 McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Serial Interface (MCSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Camera Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Controller Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multimedia Card/Secure Digital (MMC/SD) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Serial Bus (USB) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MICROWIRE Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDQ/1-Wire Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 130 130 137 141 141 145 149 151 152 154 156 157 158 159 161 164 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 6 7 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . August 2002 - Revised August 2004 SPRS197D 7 Contents 8 SPRS197D August 2002 - Revised August 2004 Figures List of Figures Figure 2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 OMAP5910 GZG MicroStar BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 GDY Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP MMU Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP MMU On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Connections for a Typical System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Connections for a System With 1.8-V SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External RC Circuit for DPLL CVDD Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tester Pin Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-kHz Oscillator External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-kHz Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal System Oscillator External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Core Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous 32-Bit Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Read - Page Mode ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-Bit (2 x 16-Bit) SDRAM RD (Read) Command (Active Row) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-Bit (2 x 16-Bit) SDRAM WRT (Write) Command (Active Row) . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM ACTV (Activate Row) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM DCAB (Precharge/Deactivate Row) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM REFR (Refresh) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM MRS (Mode Register Set) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . MCSI Master Mode Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCSI Slave Mode Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Camera Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TFT Mode (LCD.HS/LCD.VS on Falling and LCD.Px on Rising LCD.PCLK) . . . . . . . . . . . . . . . . . . TFT Mode (LCD.HS/LCD.VS on Rising and LCD.Px on Falling LCD.PCLK) . . . . . . . . . . . . . . . . . . MMC/SD Host Command Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18 21 47 55 56 69 70 71 124 125 126 126 128 129 132 133 134 135 136 138 138 139 139 140 140 144 144 145 146 147 148 150 150 151 152 153 154 August 2002 - Revised August 2004 SPRS197D 9 Figures 5-30 5-31 5-32 5-33 5-34 5-35 5-36 5-37 5-38 5-39 MMC/SD Card Response Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SD Host Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SD Host Read and Card CRC Status Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Integrated Transceiver Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MICROWIRE Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 HDQ Interface Reading From HDQ Slave Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 HDQ Interface Writing to HDQ Slave Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Communication Between OMAP5910 HDQ and HDQ Slave . . . . . . . . . . . . . . . . . . . . . . . . . HDQ/1-Wire Break (Reset) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 155 155 156 157 158 160 160 160 160 10 SPRS197D August 2002 - Revised August 2004 Tables List of Tables Table 2-1 2-2 2-3 2-4 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-33 3-34 3-35 3-36 3-37 3-38 3-39 3-40 3-41 GZG BGA Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GDY BGA Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminal Characteristics and Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 MPU Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Private Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Public Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU/DSP Shared Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Public Peripheral Registers (Accessible via MPUI Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Private Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Public Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP/MPU Shared Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Timer 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Timer 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Level 1 Interrupt Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Level 2 Interrupt Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System DMA Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MICROWIRE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDQ/1-Wire Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Host Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Camera Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU I/O/Keyboard Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Pulse Generator 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Pulse Generator 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32k Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame Adjustment Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP 5910 Pin Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus MMU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP MMU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18 22 25 34 50 51 51 51 52 52 52 53 53 54 54 54 54 72 72 72 72 73 74 75 78 80 80 81 81 82 83 85 85 86 86 86 86 86 86 87 87 89 89 90 91 August 2002 - Revised August 2004 SPRS197D 11 Tables Table 3-42 3-43 3-44 3-45 3-46 3-47 3-48 3-49 3-50 3-51 3-52 3-53 3-54 3-55 3-56 3-57 3-58 3-59 3-60 3-61 3-62 3-63 3-64 3-65 3-66 3-67 3-68 3-69 3-70 3-71 3-72 3-73 3-74 3-75 3-76 3-77 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 MPUI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIPB (Private) Bridge 1 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIPB (Public) Bridge 2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU UART TIPB Bus Switch Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Traffic Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Clock/Reset/Power Mode Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPLL1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ultra Low-Power Device Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Die Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Identification Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP DMA Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Timer 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Timer 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Interrupt Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Level 2 Interrupt Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCSI1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCSI2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Instruction Cache Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP EMIF Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP TIPB Bridge Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP UART TIPB Bus Switch Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Clock Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART3/IrDA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU/DSP Shared GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU/DSP Shared Mailbox Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Level 1 and Level 2 Interrupt Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Level 1 Interrupt Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Level 2 Interrupt Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Request Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP DMA Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-kHz Oscillator Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-kHz Input Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Base Oscillator Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Clock Speed Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 Device Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 Device Reset Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU_RST Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU_RST Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 91 91 92 92 93 93 93 94 94 94 96 99 99 99 99 99 100 101 102 104 105 106 106 106 107 107 109 110 111 112 112 113 115 116 117 118 124 125 126 127 127 128 128 129 129 12 SPRS197D August 2002 - Revised August 2004 Tables Table 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 EMIFS/Flash Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/Flash Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFF/SDRAM Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFF/SDRAM Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . . MCSI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCSI Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Camera Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Controller Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SD Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SD Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Signals (I2C.SDA and I2C.SCL) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Integrated Transceiver Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . MICROWIRE Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MICROWIRE Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDQ/1-Wire Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDQ/1-Wire Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 130 131 137 137 141 143 145 145 146 146 147 147 148 148 149 149 151 152 154 154 156 157 158 158 159 159 August 2002 - Revised August 2004 SPRS197D 13 Tables 14 SPRS197D August 2002 - Revised August 2004 Features 1 OMAP5910 Features D Low-Power, High-Performance CMOS Technology - 0.13-m Technology - 1.6-V Core Voltage TI925T (MPU) ARM9TDMI Core - Support 32-Bit and 16-Bit (Thumb Mode) Instruction Sets - 16K-Byte Instruction Cache - 8K-Byte Data Cache - Data and Program Memory Management Units (MMUs) - Two 64-Entry Translation Look-Aside Buffers (TLBs) for MMUs - 17-Word Write Buffer TMS320C55x (C55x) DSP Core - One/Two Instructions Executed per Cycle - Dual Multipliers (Two MultiplyAccumulates per Cycle) - Two Arithmetic/Logic Units - One Internal Program Bus - Five Internal Data/Operand Buses (3 Read Buses and 2 Write Buses) - 32K x 16-Bit On-Chip Dual-Access RAM (DARAM) (64K Bytes) - 48K x 16-Bit On-Chip Single-Access RAM (SARAM) (96K Bytes) - 16K x 16-Bit On-Chip ROM (32K Bytes) - Instruction Cache (24K Bytes) - Video Hardware Accelerators for DCT, iDCT, Pixel Interpolation, and Motion Estimation for Video Compression 192K Bytes of Shared Internal SRAM Memory Traffic Controller (TC) - 16-Bit EMIFS External Memory Interface to Access up to 128M Bytes of Flash, ROM, or ASRAM - 16-Bit EMIFF External Memory Interface to Access up to 64M Bytes of SDRAM 9-Channel System DMA Controller DSP Memory Management Unit Endianism Conversion Logic Digital Phase-Locked Loop (DPLL) for MPU/DSP/TC Clocking Control D DSP Peripherals - - - - D D D D D D D D D D D D D D TMS320C55x and C55x are trademarks of Texas Instruments. ARM9TDMI is a trademark of ARM Limited. Thumb is a registered trademark of ARM Limited. MICROWIRE is a trademark of National Semiconductor Corporation. 1-Wire is a registered trademark of Dallas Semiconductor Corporation. IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture. August 2002 - Revised August 2004 Three 32-Bit Timers and Watchdog Timer Level1/Level2 Interrupt Handlers Six-Channel DMA Controller Two Multichannel Buffered Serial Ports (McBSP) - Two Multichannel Serial Interfaces (MCSI) TI925T Peripherals - Three 32-Bit Timers and Watchdog Timer - 32-kHz Timer - Level1/Level2 Interrupt Handlers - USB (Full/Low Speed) Host Interface With up to 3 Ports - USB (Full Speed) Function Interface - One Integrated USB Transceiver for Either Host or Function - Multichannel Buffered Serial Port - Inter-Integrated Circuit (I2C) Master and Slave Interface - MICROWIRE Serial Interface - Multimedia Card (MMC) and Secure Digital (SD) Interface - HDQ/1-Wire Interface - Camera Interface for CMOS Sensors - ETM9 Trace Module for TI925T Debug - Keyboard Matrix Interface (6 x 5 or 8 x 8) - Up to Ten MPU General-Purpose I/Os - Pulse-Width Tone (PWT) Interface - Pulse-Width Light (PWL) Interface - Two LED Pulse Generators (LPGs) - Real-Time Clock (RTC) - LCD Controller With Dedicated System DMA Channel Shared Peripherals - Three Universal Asynchronous Receiver/Transmitters (UARTs) (One Supporting SIR Mode for IrDA) - Four Interprocessor Mailboxes - Up to 14 Shared General-Purpose I/Os Individual Power-Saving Modes for MPU/DSP/TC On-Chip Scan-Based Emulation Logic IEEE Std 1149.1 (JTAG) Boundary Scan Logic Two 289-Ball Ball Grid Array Package Options (GZG and GDY Suffixes) SPRS197D 15 Introduction 2 Introduction This section describes the main features of the OMAP5910 device, lists the terminal assignments, and describes the function of each terminal. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging. 2.1 Description The OMAP5910 is a highly integrated hardware and software platform, designed to meet the application processing needs of next-generation embedded devices. The OMAP platform enables OEMs and ODMs to quickly bring to market devices featuring rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture provides benefits of both DSP and RISC technologies, incorporating a TMS320C55x DSP core and a high-performance TI925T ARM core. The OMAP5910 device is designed to run leading open and embedded RISC-based operating systems, as well as the Texas Instruments (TI) DSP/BIOS software kernel foundation, and is available in a 289-ball MicroStar BGA package. The OMAP5910 is targeted at the following applications: * * Applications processing devices Mobile communications - - - - - * * * * * * 802.11 Bluetooth wireless technology GSM (including GPRS and EDGE) CDMA Proprietary government and other Video and image processing (MPEG4, JPEG, Windows Media Video, etc.) Advanced speech applications (text-to-speech, speech recognition) Audio processing (MPEG-1 Audio Layer3 [MP3], AMR, WMA, AAC, and other GSM speech codecs) Graphics and video acceleration Generalized web access Data processing (fax, encryption/decryption, authentication, signature verification and watermarking) 2.1.1 TMS320C55x DSP Core The DSP core of the OMAP5910 device is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity. OMAP, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments. Bluetooth is a trademark owned by Bluetooth SIG, Inc. Windows is a registered trademark of Microsoft Corporation. Other trademarks are the property of their respective owners. 16 SPRS197D August 2002 - Revised August 2004 Introduction The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the address unit (AU) and data unit (DU) of the C55x CPU. The C55x DSP generation supports a variable byte width instruction set for improved code density. The instruction unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the program unit (PU). The program unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The OMAP5910 DSP core also includes a 24K-byte instruction cache to minimize external memory accesses, improving data throughput and conserving system power. 2.1.1.1 DSP Tools Support The 55x DSP core is supported by the industry's leading eXpressDSP software environment including the Code Composer Studio integrated development environment, DSP/BIOS software kernel foundation, the TMS320 DSP Algorithm Standard, and the industry's largest third-party network. Code Composer Studio features code generation tools including a C-Compiler, Visual Linker, simulator, Real-Time Data Exchange (RTDX), XDS510 emulation device drivers, and Chip Support Libraries (CSL). DSP/BIOS is a scalable real-time software foundation available for no cost to users of Texas Instruments' DSP products providing a preemptive task scheduler and real-time analysis capabilities with very low memory and megahertz overhead. The TMS320 DSP Algorithm Standard is a specification of coding conventions allowing fast integration of algorithms from different teams, sites, or third parties into the application framework. Texas Instruments' extensive DSP third-party network of over 400 providers brings focused competencies and complete solutions to customers. 2.1.1.2 DSP Software Support Texas Instruments has also developed foundation software available for the 55x DSP core. The C55x DSP Library (DSPLIB) features over 50 C-callable software kernels (FIR/IIR filters, Fast Fourier Transforms (FFTs), and various computational functions). The DSP Image/Video Processing Library (IMGLIB) contains over 20 software kernels highly optimized for C55x DSPs and is compiled with the latest revision of the C55x DSP code generation tools. These imaging functions support a wide range of applications that include compression, video processing, machine vision, and medical imaging. 2.1.2 TI-Enhanced TI925T RISC Processor The MPU core is a TI925T reduced instruction set computer (RISC) processor. The TI925T is a 32-bit processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The MPU core incorporates: * * * * A coprocessor 15 (CP15) and protection module Data and program Memory Management Units (MMUs) with table look-aside buffers. A separate 16K-byte instruction cache and 8K-byte data cache. Both are two-way associative with virtual index virtual tag (VIVT). A 17-word write buffer (WB) The OMAP5910 device uses the TI925T core in little endian mode only. To reduce effective memory access time, the TI925T has an instruction cache, a data cache, and a write buffer. In general, these are transparent to program execution. eXpressDSP, Code Composer Studio, TMS320, RTDX, and XDS510 are trademarks of Texas Instruments. August 2002 - Revised August 2004 SPRS197D 17 Introduction 2.2 Terminal Assignments Figure 2-1 illustrates the ball locations for the 289-ball GZG ball grid array (BGA) package and is used in conjunction with Table 2-1 to locate signal names and ball grid numbers. GZG BGA ball numbers in Table 2-1 are read from left-to-right, top-to-bottom. Y V T P M K H F D B AA W U R N L J G E C A 1 2 3 4 5 6 7 9 11 13 15 17 19 21 8 10 12 14 16 18 20 Figure 2-1. OMAP5910 GZG MicroStar BGA Package (Bottom View) In Table 2-1, signals with multiplexed functions are separated with forward slashes as follows: * signal1/signal2/signal3 (for example, GPIO11/HDQ) Signals which are associated with specific peripherals are denoted by using the peripheral name, followed by a period, and then the signal name; as follows: * GZG BGA BALL # A1 A7 A15 A21 B4 B8 B13 B17 B21 C4 C8 C12 peripheral1.signal1 (for example, MCBSP1.DR) Table 2-1. GZG BGA Terminal Assignments SIGNAL DVDD4 DVDD4 DVDD1 VSS SDRAM.D[13] SDRAM.D[4] CVDD3 LCD.P[11] LCD.P[1] SDRAM.D[14] SDRAM.D[2] SDRAM.A[7] GZG BGA BALL # A2 A9 A17 B1 B5 B9 B14 B18 C1 C5 C9 C13 SIGNAL SDRAM.RAS CVDD LCD.P[13] VSS VSS SDRAM.D[0] SDRAM.A[0] VSS FLASH.A[3] SDRAM.D[11] SDRAM.CLK SDRAM.A[4] GZG BGA BALL # A3 A11 A19 B2 B6 B10 B15 B19 C2 C6 C10 C14 SIGNAL CVDD1 VSS DVDD1 VSS SDRAM.D[8] DVDD4 LCD.AC LCD.P[6] DVDD5 SDRAM.D[9] SDRAM.BA[0] SDRAM.A[1] GZG BGA BALL # A5 A13 A20 B3 B7 B12 B16 B20 C3 C7 C11 C15 SIGNAL DVDD4 VSS LCD.P[5] SDRAM.DQML VSS DVDD4 VSS CVDD3 SDRAM.WE SDRAM.D[6] SDRAM.A[10] LCD.PCLK See Section 5.6.1 and Section 5.6.2 for special VSS considerations with ocillator circuits. MicroStar BGA is a trademark of Texas Instruments. 18 SPRS197D August 2002 - Revised August 2004 Introduction Table 2-1. GZG BGA Terminal Assignments (Continued) GZG BGA BALL # C16 C20 D4 D8 D12 D16 D20 E4 E20 F4 G1 G8 G12 G19 H3 H9 H13 H19 J3 J14 J20 K4 K15 L1 L8 SIGNAL LCD.P[14] KB.C[5] SDRAM.DQMU SDRAM.D[5] SDRAM.A[6] LCD.P[9] KB.C[1] FLASH.A[4] KB.R[3] FLASH.A[6] VSS SDRAM.D[3] SDRAM.A[2] PWRON_RESET FLASH.A[15] SDRAM.CAS LCD.P[4] CAM.EXCLK/ ETM.SYNC/ UWIRE.SDO FLASH.A[19] CAM.D[5]/ ETM.D[5]/ UWIRE.SDI VSS FLASH.A[22] CAM.D[2]/ ETM.D[2]/ UART3.CTS DVDD5 FLASH.A[21] CAM.D[0]/ ETM.D[0]/ MPUIO12 FLASH.CS2/ FLASH.BAA GPIO7/ MMC.DAT2 VSS FLASH.D[2] GPIO12/ MCBSP3.FSX FLASH.D[3] GZG BGA BALL # C17 C21 D5 D9 D13 D17 E1 E5 E21 F18 G2 G9 G13 G20 H4 H10 H14 H20 J4 J15 J21 K7 K18 L3 L14 SIGNAL LCD.P[10] KB.C[4] SDRAM.D[15] SDRAM.CKE SDRAM.A[3] LCD.P[8] DVDD5 RSVD DVDD1 KB.C[0] FLASH.A[12] SDRAM.D[1] LCD.P[12] MCBSP1.CLKS FLASH.A[14] SDRAM.A[11] KB.R[2] MCBSP1.DR FLASH.A[18] CAM.LCLK/ ETM.CLK/ UWIRE.SCLK CVDD3 FLASH.A[16] CAM.D[4]/ ETM.D[4]/ UART3.TX FLASH.BE[0] UART3.RX/PWL/ UART2.RX DVDD1 FLASH.CS0 UART3.TX/ PWT/ UART2.TX FLASH.D[1] FLASH.CS3 GPIO13/ KB.R[5] DVDD5 GZG BGA BALL # C18 D2 D6 D10 D14 D18 E2 E18 F2 F19 G3 G10 G14 G21 H7 H11 H15 J1 J7 J18 K2 K8 K19 L4 L15 SIGNAL LCD.P[7] FLASH.A[5] SDRAM.D[12] SDRAM.BA[1] LCD.VS LCD.P[0] VSS KB.C[3] CVDD KB.R[1] FLASH.A[11] SDRAM.A[12] LCD.P[3] MCBSP1.CLKX FLASH.RDY SDRAM.A[5] MCBSP1.FSX/ MCBSP1.DX FLASH.A[20] FLASH.A[8] CAM.D[7]/ ETM.D[7]/ UWIRE.CS0 VSS FLASH.A[13] CAM.D[3]/ ETM.D[3]/ UART3.RX FLASH.ADV CAM.HS/ ETM.PSTAT[1]/ UART2.CTS CVDD4 FLASH.BE[1] CAM.RSTZ/ ETM.PSTAT[0]/ UART2.RTS FLASH.CLK UWIRE.CS0/ MCBSP3.CLKX GPIO11/ HDQ FLASH.D[4] GZG BGA BALL # C19 D3 D7 D11 D15 D19 E3 E19 F3 F20 G4 G11 G18 H2 H8 H12 H18 J2 J8 J19 K3 K14 K20 L7 L18 SIGNAL LCD.P[2] FLASH.A[2] SDRAM.D[7] SDRAM.A[9] LCD.P[15] KB.C[2] FLASH.A[7] KB.R[4] FLASH.A[9] VSS FLASH.A[10] SDRAM.A[8] KB.R[0] DVDD5 SDRAM.D[10] LCD.HS MCBSP1.DX/ MCBSP1.FSX FLASH.A[17] FLASH.A[1] CAM.D[6]/ ETM.D[6]/ UWIRE.CS3 FLASH.A[23] CAM.D[1]/ETM.D[1]/ UART3.RTS VSS FLASH.A[24] CAM.VS/ ETM.PSTAT[2] FLASH.CS1 GPIO2/ SPI.CLK GPIO15/ KB.R[7] FLASH.D[0] MPUIO2/ EXT_DMA_REQ0 GPIO14/ KB.R[6] FLASH.D[5] L19 M4 M15 N1 N7 N18 P2 L21 M7 M18 N2 N8 N19 P3 M2 M8 M19 N3 N14 N20 P4 M3 M14 M20 N4 N15 N21 P7 See Section 5.6.1 and Section 5.6.2 for special VSS considerations with ocillator circuits. August 2002 - Revised August 2004 SPRS197D 19 Introduction Table 2-1. GZG BGA Terminal Assignments (Continued) GZG BGA BALL # P8 P12 SIGNAL FLASH.D[11] CVDD GPIO3/ SPI.CS3/ MCBSP3.FSX/LED1 FLASH.D[6] UART2.RX/ USB2.VM BCLKREQ/ UART3.CTS/ UART1.DSR CVDD3 FLASH.D[14] FLASH.D[12] UWIRE.SDI/ UART3.DSR/ UART1.DSR/ MCBSP3.DR DVDD5 UART2.TX/ USB2.TXD MMC.DAT1/ MPUIO7 UART1.RX CONF FLASH.WE MCBSP2.FSR/ GPIO12 MMC.DAT2/ MPUIO11 MCSI1.DOUT/ USB1.TXD TCK CVDD2 UART2.CTS/ USB2.RCV/ GPIO7 MCLK UART1.TX GZG BGA BALL # P9 P13 SIGNAL USB.DP CLK32K_IN GPIO6/ SPI.CS1/ MCBSP3.FSX FLASH.D[7] MCLKREQ/EXT_ MASTER_REQ UART1.CTS VSS I2C.SCL VSS MPUIO1 FLASH.D[15] MCBSP2.CLKR/ GPIO11 MMC.CLK MPU_RST UWIRE.SCLK/ KB.C[7] OSC1_OUT MCBSP2.FSX MMC.DAT3/ MPUIO6 RST_OUT BFAIL/ EXT_FIQ OSC1_IN MCBSP2.CLKX MCSI2.CLK/ USB2.SUSP VSS GZG BGA BALL # P10 P14 SIGNAL MCBSP2.DR/ MCBSP2.DX RST_HOST_OUT/ MCBSP3.DX/ USB1.SE0 GPIO4/ SPI.CS2/ MCBSP3.FSX FLASH.D[8] MMC.DAT0/SPI.DI GPIO0/ SPI.RDY/ USB.VBUS FLASH.D[9] MPUIO4/ EXT_DMA_REQ1/ LED2 FLASH.D[13] VSS FLASH.WP MPUIO3 VSS EMU0 I2C.SDA USB.PUEN/ USB.CLKO GPIO9 OSC32K_IN MCBSP3.CLKX/ USB1.TXEN VSS VSS DVDD3 CLK32K_OUT/ MPUIO0/ USB1.SPEED DVDD1 GZG BGA BALL # P11 P15 SIGNAL MMC.CMD/SPI.DO UWIRE.CS3/ KB.C[6] DVDD5 USB.DM OSC32K_OUT GPIO1/ UART3.RTS FLASH.D[10] MPUIO5/ LOW_PWR FLASH.OE DVDD1 VSS MCSI2.SYNC/ GPIO7 MCSI1.SYNC/ USB1.VP TMS FLASH.RP UART2.RTS/ USB2.SE0/ MPUIO5 MCSI2.DOUT/ USB2.TXEN MCSI1.DIN/ USB1.RCV EMU1 UWIRE.SDO/ UART3.DTR/ UART1.DTR/ MCBSP3.DX UART2.BCLK GPIO8 BCLK/ UART3.RTS/ UART1.DTR STAT_VAL/ WKUP P18 R2 R9 R13 R20 T4 U1 U18 V2 V6 V10 V14 V18 W2 W6 W10 W14 P19 R3 R10 R14 R21 T18 U2 U19 V3 V7 V11 V15 V19 W3 W7 W11 W15 P20 R4 R11 R18 T2 T19 U3 U20 V4 V8 V12 V16 V20 W4 W8 W12 W16 R1 R8 R12 R19 T3 T20 U4 U21 V5 V9 V13 V17 W1 W5 W9 W13 W17 W18 Y1 Y5 W19 Y2 Y6 W20 Y3 Y7 W21 Y4 Y8 Y9 Y14 Y10 Y15 Y12 Y16 Y13 Y17 See Section 5.6.1 and Section 5.6.2 for special VSS considerations with ocillator circuits. 20 SPRS197D August 2002 - Revised August 2004 Introduction Table 2-1. GZG BGA Terminal Assignments (Continued) GZG BGA BALL # Y18 AA1 AA7 AA15 AA21 SIGNAL TRST VSS VSS UART1.RTS VSS GZG BGA BALL # Y19 AA2 AA9 AA17 SIGNAL TDI DVDD2 MCSI2.DIN/ USB2.VP MPU_BOOT/ MCBSP3.DR/ USB1.SUSP GZG BGA BALL # Y20 AA3 AA11 AA19 SIGNAL CVDD CVDD2 DVDD1 TDO GZG BGA BALL # Y21 AA5 AA13 AA20 SIGNAL CVDDA MCBSP2.DX/ MCBSP2.DR MCSI1.CLK/ USB1.VM CLK32K_CTRL See Section 5.6.1 and Section 5.6.2 for special VSS considerations with ocillator circuits. Figure 2-2 illustrates the ball locations for the 289-ball GDY ball grid array (BGA) package and is used in conjunction with Table 2-1 to locate signal names and ball grid numbers. GDY BGA ball numbers in Figure 2-2 are read from left-to-right, top-to-bottom. U T R P N M L K J H G F E D C B A 1 3 5 7 9 11 13 15 17 2 4 6 8 10 12 14 16 Bottom View Figure 2-2. OMAP5910 GDY Package (Bottom View) In Table 2-2, signals with multiplexed functions are separated with forward slashes as follows: * signal1/signal2/signal3 (for example, GPIO11/HDQ) Signals which are associated with specific peripherals are denoted by using the peripheral name, followed by a period, and then the signal name; as follows: * peripheral1.signal1 (for example, MCBSP1.DR) August 2002 - Revised August 2004 SPRS197D 21 Introduction Table 2-2. GDY BGA Terminal Assignments GDY BGA BALL # A1 A5 A9 A13 A17 B4 B8 B12 B16 C3 C7 C11 C15 D2 D6 D10 D14 E1 E5 E9 E13 E17 F4 F8 F12 F16 G3 G7 G11 SIGNAL SDRAM.WE DVDD4 SDRAM.A[5] LCD.P[9] KB.C[5] SDRAM.D[12] SDRAM.BA[0] LCD.P[13] LCD.P[0] FLASH.RDY SDRAM.D[3] SDRAM.A[3] LCD.P[5] FLASH.A[7] SDRAM.D[7] SDRAM.A[4] KB.R[1] FLASH.A[12] VSS SDRAM.A[10] VSS KB.R[3] FLASH.A[10] SDRAM.CAS VSS MCBSP1.FSX/ MCBSP1.DX FLASH.A[14] VSS VSS GDY BGA BALL # A2 A6 A10 A14 B1 B5 B9 B13 B17 C4 C8 C12 C16 D3 D7 D11 D15 E2 E6 E10 E14 F1 F5 F9 F13 F17 G4 G8 G12 SIGNAL SDRAM.DQMU SDRAM.D[0] SDRAM.A[1] DVDD1 FLASH.A[1] SDRAM.D[11] SDRAM.A[11] LCD.P[11] KB.C[3] SDRAM.RAS SDRAM.A[12] DVDD1 LCD.P[1] DVDD4 SDRAM.CKE LCD.VS LCD.P[2] CVDD SDRAM.D[8] DVDD4 DVDD1 DVDD5 FLASH.A[8] SDRAM.A[7] MCBSP1.CLKS MCBSP1.DX/ MCBSP1.FSX FLASH.A[13] SDRAM.D[13] CAM.D[6]/ ETM.D[6]/ UWIRE.CS3 MCBSP1.DR FLASH.A[18] DVDD5 CVDD3 CAM.LCLK/ ETM.CLK/ UWIRE.SCLK FLASH.CS0 VSS GDY BGA BALL # A3 A7 A11 A15 B2 B6 B10 B14 C1 C5 C9 C13 C17 D4 D8 D12 D16 E3 E7 E11 E15 F2 F6 F10 F14 G1 G5 G9 G13 SIGNAL SDRAM.D[9] SDRAM.CLK LCD.AC LCD.P[6] SDRAM.DQML SDRAM.D[5] SDRAM.A[2] LCD.P[7] FLASH.A[3] SDRAM.D[14] SDRAM.BA[1] LCD.P[14] KB.C[0] SDRAM.D[15] DVDD4 LCD.P[15] KB.C[4] FLASH.A[5] SDRAM.D[1] LCD.HS KB.C[2] FLASH.A[11] VSS CVDD3 PWRON_RESET FLASH.A[16] FLASH.A[15] VSS CAM.EXCLK/ ETM.SYNC/ UWIRE.SDO CAM.D[3]/ ETM.D[3]/ UART3.RX FLASH.A[19] VSS UART3.RX/PWL/ UART2.RX CAM.D[5]/ ETM.D[5]/ UWIRE.SDI FLASH.A[24] VSS GDY BGA BALL # A4 A8 A12 A16 B3 B7 B11 B15 C2 C6 C10 C14 D1 D5 D9 D13 D17 E4 E8 E12 E16 F3 F7 F11 F15 G2 G6 G10 G14 SIGNAL SDRAM.D[6] SDRAM.A[9] LCD.PCLK LCD.P[3] CVDD1 SDRAM.D[2] SDRAM.A[0] LCD.P[4] FLASH.A[4] SDRAM.D[10] SDRAM.A[8] LCD.P[8] DVDD5 DVDD4 SDRAM.A[6] KB.R[0] KB.R[4] FLASH.A[6] CVDD LCD.P[10] KB.C[1] FLASH.A[9] SDRAM.D[4] LCD.P[12] KB.R[2] FLASH.A[17] FLASH.A[2] CVDD3 CAM.D[7]/ ETM.D[7]/ UWIRE.CS0 FLASH.ADV FLASH.A[21] VSS DVDD1 CAM.D[2]/ ETM.D[2]/ UART3.CTS FLASH.A[23] VSS G15 H2 H6 H10 H14 J1 J5 MCBSP1.CLKX FLASH.A[20] FLASH.A[22] VSS CAM.D[1]/ETM.D[1]/ UART3.RTS FLASH.BE[1] FLASH.BE[0] G16 H3 H7 H11 H15 J2 J6 G17 H4 H8 H12 H16 J3 J7 H1 H5 H9 H13 H17 J4 J8 See Section 5.6.1 and Section 5.6.2 for special VSS considerations with ocillator circuits. 22 SPRS197D August 2002 - Revised August 2004 Introduction Table 2-2. GDY BGA Terminal Assignments (Continued) GDY BGA BALL # J9 J13 J17 K4 K8 K12 K16 L3 L7 SIGNAL VSS UART3.TX/ PWT/ UART2.TX CAM.VS/ ETM.PSTAT[2] FLASH.CLK VSS GPIO3/ SPI.CS3/ MCBSP3.FSX/LED1 GPIO15/ KB.R[7] DVDD5 VSS GDY BGA BALL # J10 J14 K1 K5 K9 K13 K17 L4 L8 SIGNAL VSS CAM.RSTZ/ ETM.PSTAT[0]/ UART2.RTS FLASH.CS1 FLASH.CS2/ FLASH.BAA VSS GPIO6/ SPI.CS1/ MCBSP3.FSX GPIO14/ KB.R[6] FLASH.D[2] CVDD2 UWIRE.CS3/ KB.C[6] GPIO11/ HDQ FLASH.D[11] UART2.RX/ USB2.VM RST_OUT GPIO2/ SPI.CLK FLASH.D[13] UART2.CTS/ USB2.RCV/ GPIO7 CLK32K_OUT/ MPUIO0/ USB1.SPEED I2C.SDA FLASH.D[10] USB.DP DVDD1 UART1.TX GDY BGA BALL # J11 J15 K2 K6 K10 K14 L1 L5 L9 SIGNAL VSS CAM.D[4]/ ETM.D[4]/ UART3.TX CVDD4 DVDD5 VSS GPIO13/ KB.R[5] FLASH.CS3 FLASH.D[0] VSS MPUIO5/ LOW_PWR GPIO7/ MMC.DAT2 FLASH.D[6] GPIO9 VSS GPIO0/ SPI.RDY/ USB.VBUS FLASH.OE DVDD3 GDY BGA BALL # J12 J16 K3 K7 K11 K15 L2 L6 L10 SIGNAL VSS CAM.D[0]/ ETM.D[0]/ MPUIO12 FLASH.D[1] CVDD2 CVDD3 CAM.HS/ ETM.PSTAT[1]/ UART2.CTS DVDD5 FLASH.D[3] BCLKREQ/ UART3.CTS/ UART1.DSR GPIO4/ SPI.CS2/ MCBSP3.FSX FLASH.D[4] FLASH.D[7] MMC.DAT1/ MPUIO7 UWIRE.SCLK/ KB.C[7] GPIO1/ UART3.RTS FLASH.D[8] MCLKREQ/ EXT_MASTER_REQ MCSI1.DOUT/ USB1.TXD DVDD1 OSC1_OUT MPUIO3 BCLK/ UART3.RTS/ UART1.DTR I2C.SCL L11 L15 M2 M6 M10 M14 N1 N5 VSS GPIO12/ MCBSP3.FSX FLASH.D[5] VSS UART1.CTS MPUIO1 FLASH.D[9] VSS L12 L16 M3 M7 M11 M15 N2 N6 L13 L17 M4 M8 M12 M16 N3 N7 L14 M1 M5 M9 M13 M17 N4 N8 N9 CLK32K_IN N10 N11 RSVD MPUIO4/ EXT_DMA_REQ1/ LED2 FLASH.WE MCBSP2.FSR/ GPIO12 CVDD MCBSP3.CLKX/ USB1.TXEN N12 N13 N17 P4 P8 P12 VSS MPUIO2/ EXT_DMA_REQ0 USB.DM MCSI2.DIN/ USB2.VP MPU_RST N14 P1 P5 P9 P13 N15 P2 P6 P10 P14 N16 P3 P7 P11 P15 See Section 5.6.1 and Section 5.6.2 for special VSS considerations with ocillator circuits. August 2002 - Revised August 2004 SPRS197D 23 Introduction Table 2-2. GDY BGA Terminal Assignments (Continued) GDY BGA BALL # P16 SIGNAL UWIRE.SDO/ UART3.DTR/ UART1.DTR/ MCBSP3.DX FLASH.WP MCSI2.SYNC/ GPIO7 UART1.RX CVDDA FLASH.RP MCBSP2.FSX OSC32K_IN TCK DVDD5 MCBSP2.CLKX MMC.DAT0/SPI.DI RST_HOST_OUT/ MCBSP3.DX/ USB1.SE0 TDI GDY BGA BALL # P17 SIGNAL UWIRE.SDI/ UART3.DSR/ UART1.DSR/ MCBSP3.DR UART2.TX/ USB2.TXD MMC.DAT2/ MPUIO11 MPU_BOOT/ MCBSP3.DR/ USB1.SUSP UWIRE.CS0/ MCBSP3.CLKX USB.PUEN/ USB.CLKO MCSI2.DOUT/ USB2.TXEN MCSI1.SYNC/ USB1.VP CLK32K_CTRL FLASH.D[15] GPIO8 MMC.CLK STAT_VAL/ WKUP GDY BGA BALL # R1 SIGNAL GDY BGA BALL # R2 SIGNAL FLASH.D[12] MCBSP2.DX/ MCBSP2.DR MMC.DAT3/ MPUIO6 TMS EMU0 UART2.BCLK MCSI2.CLK/ USB2.SUSP DVDD1 CONF DVDD2 MCLK MCSI1.CLK/ USB1.VM TRST OSC1_IN MCBSP2.DR/ MCBSP2.DX MCSI1.DIN/ USB1.RCV BFAIL/ EXT_FIQ FLASH.D[14] MCBSP2.CLKR/ GPIO11 OSC32K_OUT EMU1 CVDD UART2.RTS/ USB2.SE0/ MPUIO5 MMC.CMD/SPI.DO UART1.RTS TDO R3 R7 R11 R15 T2 T6 T10 T14 U1 U5 U9 U13 U17 R4 R8 R12 R16 T3 T7 T11 T15 U2 U6 U10 U14 R5 R9 R13 R17 T4 T8 T12 T16 U3 U7 U11 U15 R6 R10 R14 T1 T5 T9 T13 T17 U4 U8 U12 U16 See Section 5.6.1 and Section 5.6.2 for special VSS considerations with ocillator circuits. 2.3 Terminal Characteristics and Multiplexing Table 2-3 describes terminal characteristics and the signals multiplexed on each ball. The table column headers are explained below: * * * SIGNAL NAME: The names of all the signals that are multiplexed on each ball. TYPE: The terminal type when a particular signal is multiplexed on the terminal. MUX CTRL SETTING: The register field that controls multiplexing on the terminal and the proper register field setting necessary to select the signal to be multiplexed on the terminal. The reset values of these register fields are indicated in bold type. DESELECTED INPUT STATE: The logic level internally driven to the signal when it is not selected to be multiplexed on the corresponding terminal. PULLUP/PULLDN: Denotes the presence of an internal pullup or pulldown. Pullups and pulldowns can be enabled or disabled via software. BUFFER STRENGTH: Drive strength of the associated output buffer. * * * 24 SPRS197D August 2002 - Revised August 2004 Introduction * OTHER: Contains various terminal information, such as buffer type, boundary scan capability, and gating/inhibit functionality. Certain terminals may be gated or 3-stated based on the state of other terminals and/or software configuration register settings. RESET STATE: The state of the terminal at reset. SUPPLY: The voltage supply which powers the terminal's I/O buffers. NOTE: Due to the extensive pin multiplexing options which are available on the OMAP5910 device, a software utility is available to ease the process of configuring the pins based on the peripheral set required by a specific application. The 5910 OMAP Pin Configuration Utility is currently available from Texas Instruments. NOTE: Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily avoided with proper software configuration. Table 2-3. Terminal Characteristics and Multiplexing * * GZG BALL C3 A2 D4 B3 D5 C4 B4 D6 C5 H8 C6 B6 D7 C7 D8 B8 G8 C8 G9 B9 D9 C9 H9 D10 C10 GDY BALL A1 C4 A2 B2 D4 C5 G8 B4 B5 C6 A3 E6 D6 A4 B6 F7 C7 B7 E7 A6 D7 A7 F8 C9 B8 SIGNAL NAME SDRAM.WE SDRAM.RAS SDRAM.DQMU SDRAM.DQML SDRAM.D[15:0] TYPE O/Z O/Z O/Z O/Z I/O/Z MUX CTRL SETTING NA NA NA NA NA DESELECTED INPUT STATE NA NA NA NA NA PU/ PD BUFFER STRENGTH 4 mA 4 mA 4 mA 4 mA 4 mA OTHER A A A A E RESET STATE# 1 1 1 1 0 SUPPLY DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 SDRAM.CKE SDRAM.CLK SDRAM.CAS SDRAM.BA[1:0] O/Z I/O/Z O/Z O/Z NA NA NA NA NA NA NA NA 4 mA 8 mA 4 mA 4 mA A E A A 1 LZ 1 0 DVDD4 DVDD4 DVDD4 DVDD4 I = Input, O = Output, Z = High-Impedance 'regx' denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x PD20 = 20-A internal pulldown, PD100 = 100-A pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = Fail-safe LVCMOS input/output G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/output G3 = Terminal may be gated by BFAIL and PWRON_RESET D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Fail-safe LVCMOS input and Standard LVCMOS output J = Boundary-scannable terminal F = analog oscillator terminals # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low || UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module. August 2002 - Revised August 2004 SPRS197D 25 Introduction Table 2-3. Terminal Characteristics and Multiplexing (Continued) GZG BALL G10 H10 C11 D11 G11 C12 D12 H11 C13 D13 G12 C14 B14 D14 H12 B15 C15 D15 C16 A17 G13 B17 C17 D16 D17 C18 B19 A20 H13 G14 C19 B21 D18 C20 C21 E18 D19 D20 F18 E19 E20 H14 F19 G18 G19 G20 G21 H15 5 GDY BALL C8 B9 E9 A8 C10 F9 D9 A9 D10 C11 B10 A10 B11 D11 E11 A11 A12 D12 C13 B12 F11 B13 E12 A13 C14 B14 A15 C15 B15 A16 D15 C16 B16 A17 D16 B17 E15 E16 C17 D17 E17 F15 D14 D13 F14 F13 G15 F17 SIGNAL NAME SDRAM.A[12:0] TYPE O/Z MUX CTRL SETTING NA DESELECTED INPUT STATE NA PU/ PD BUFFER STRENGTH 4 mA OTHER A RESET STATE# 0 SUPPLY DVDD4 LCD.VS LCD.HS LCD.AC LCD.PCLK LCD.P[15:0] O O O O O NA NA NA NA NA NA NA NA NA NA 4 mA 4 mA 4 mA 4 mA 4 mA J, A, G1 J, A, G1 J, A, G1 J, A, G1 J, A, G1 0 0 0 0 0 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 KB.C[5:0] O NA NA 4 mA A, J 0 DVDD1 KB.R[4:0] I NA NA A, J input DVDD1 PWRON_RESET MCBSP1.CLKS MCBSP1.CLKX MCBSP1.FSX MCBSP1.DX I I I/O/Z I/O/Z O NA NA NA reg4[14:12] = 000 reg4[14:12] = 001 NA NA NA 0 NA 4 mA 4 mA B, J B, J J, B, G1 J, B, G , G1 input input Z Z DVDD1 DVDD1 DVDD1 DVDD1 I = Input, O = Output, Z = High-Impedance 'regx' denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x PD20 = 20-A internal pulldown, PD100 = 100-A pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = Fail-safe LVCMOS input/output G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/output G3 = Terminal may be gated by BFAIL and PWRON_RESET D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Fail-safe LVCMOS input and Standard LVCMOS output J = Boundary-scannable terminal F = analog oscillator terminals # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low || UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module. 26 SPRS197D August 2002 - Revised August 2004 Introduction Table 2-3. Terminal Characteristics and Multiplexing (Continued) GZG BALL H18 8 H20 H19 9 GDY BALL F16 6 G16 G3 G13 SIGNAL NAME MCBSP1.DX MCBSP1.FSX MCBSP1.DR CAM.EXCLK ETM.SYNC UWIRE.SDO J5 J15 H15 5 CAM.LCLK ETM.CLK UWIRE.SCLK J8 J18 G G14 CAM.D[7] ETM.D[7] UWIRE.CS0 J9 J19 G G12 CAM.D[6] ETM.D[6] UWIRE.CS3 J J14 H16 6 CAM.D[5] ETM.D[5] UWIRE.SDI K18 8 J5 J15 CAM.D[4] ETM.D[4] UART3.TX K19 9 G G17 CAM.D[3] ETM.D[3] UART3.RX K15 5 H17 CAM.D[2] ETM.D[2] UART3.CTS K14 H14 CAM.D[1] ETM.D[1] UART3.RTS L19 9 J6 J16 CAM.D[0] ETM.D[0] MPUIO12 L18 8 L15 5 J J17 K15 5 CAM.VS ETM.PSTAT[2] CAM.HS ETM.PSTAT[1] UART2.CTS TYPE O I/O/Z I O O O I O O I O O I O O I O I I O O I O I I O I I O O I O I/O/Z I O I O I MUX CTRL SETTING reg4[17:15] = 000 reg4[17:15] = 001 NA reg4[23:21] = 000 reg4[23:21] = 001 reg4[23:21] = 010 reg4[26:24] = 000 reg4[26:24] = 001 reg4[26:24] = 010 reg4[29:27] = 000 reg4[29:27] = 001 reg4[29:27] = 010 reg5[2:0] = 000 reg5[2:0] = 001 reg5[2:0] = 010 reg5[5:3] = 000 reg5[5:3] = 001 reg5[5:3] = 010 reg5[8:6] = 000 reg5[8:6] = 001 reg5[8:6] = 010 reg5[11:9] = 000 reg5[11:9] = 001 reg5[11:9] = 010 reg5[14:12] = 000 reg5[14:12] = 001 reg5[14:12] = 010 reg5[17:15] = 000 reg5[17:15] = 001 reg5[17:15] = 010 reg5[20:18] = 000 reg5[20:18] = 001 reg5[20:18] = 010 reg5[23:21] = 000 reg5[23:21] = 001 reg5[26:24] = 000 reg5[26:24] = 001 reg5[26:24] = 010 DESELECTED INPUT STATE NA 0 NA NA NA NA 0 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA PU/ PD BUFFER STRENGTH 4 mA OTHER J, B, G , G1 B,J RESET STATE# 0 input 0 SUPPLY DVDD1 DVDD1 DVDD1 PD20 8 mA J, A, G , G1 8 mA B, J , input p DVDD1 8 mA B, J , input p DVDD1 8 mA B, J , input p DVDD1 8 mA PD20 8 mA B, J , input p DVDD1 B, J , input p DVDD8 8 mA PD20 8 mA PD20 8 mA B, J , input p DVDD1 B, J , input p DVDD1 B, J , input p DVDD1 8 mA B, J , input p DVDD1 8 mA 8 mA PD20 B, J , B, J , input p input p DVDD1 DVDD1 I = Input, O = Output, Z = High-Impedance 'regx' denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x PD20 = 20-A internal pulldown, PD100 = 100-A pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = Fail-safe LVCMOS input/output G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/output G3 = Terminal may be gated by BFAIL and PWRON_RESET D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Fail-safe LVCMOS input and Standard LVCMOS output J = Boundary-scannable terminal F = analog oscillator terminals # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low || UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module. August 2002 - Revised August 2004 SPRS197D 27 Introduction Table 2-3. Terminal Characteristics and Multiplexing (Continued) GZG BALL M19 9 GDY BALL J J14 SIGNAL NAME CAM.RSTZ ETM.PSTAT[0] UART2.RTS M18 8 J3 J13 pin forced to drive low UART3.TX PWT IRQ_OBS UART2.TX L14 H12 UART3.RX PWL DMA_REQ_OBS UART2.RX M20 K16 GPIO15 KB.R[7] N21 K17 GPIO14 KB.R[6] N19 9 GPIO13 KB.R[5] N18 8 L15 5 GPIO12 MCBSP3.FSX N20 0 L16 6 GPIO11 HDQ M15 5 L17 GPIO7 MMC.DAT2 P19 9 K13 3 GPIO6 SPI.CS1 MCBSP3.FSX P20 0 L14 GPIO4 SPI.CS2 MCBSP3.FSX P18 8 K12 GPIO3 SPI.CS3 MCBSP3.FSX LED1 M14 TYPE O O O O O O O O I O O I I/O/Z I I/O/Z I I/O/Z I I/O/Z I/O/Z I/O/Z I/O I/O/Z I/O/Z I/O/Z O I/O/Z I/O/Z O I/O/Z I/O/Z O I/O/Z O I/O/Z O MUX CTRL SETTING reg5[29:27] = 000 reg5[29:27] = 001 reg5[29:27] = 010 reg6[2:0] = 000 reg6[2:0] = 001 reg6[2:0] = 010 reg6[2:0] = 011 reg6[2:0] = 100 reg6[5:3] = 000 reg6[5:3] = 001 reg6[5:3] = 010 reg6[5:3] = 011 reg6[8:6] = 000 reg6[8:6] = 001 reg6[11:9] = 000 reg6[11:9] = 001 reg6[14:12] = 000 reg6[14:12] = 001 reg6[17:15] = 000 reg6[17:15] = 001 reg6[20:18] = 000 reg6[20:18] = 001 reg6[23:21] = 000 reg6[23:21] = 001 reg6[26:24] = 000 reg6[26:24] = 001 reg6[26:24] = 010 reg6[29:27] = 000 reg6[29:27] = 001 reg6[29:27] = 010 reg7[2:0] = 000 reg7[2:0] = 001 reg7[2:0] = 010 reg7[2:0] = 011 reg7[5:3] = 000 reg7[5:3] = 001 DESELECTED INPUT STATE NA NA NA NA NA NA NA NA 1 NA NA NA NA 1 NA 1 NA 1 NA 0 NA NA NA 1 NA NA NA NA NA NA NA NA NA NA NA NA PU/ PD BUFFER STRENGTH 8 mA OTHER J, B, G , G1 RESET STATE# 0 SUPPLY DVDD1 4 mA J, A, G , G1 0 DVDD1 4 mA B, J , input p DVDD1 PD20 4 mA J, B, G1 input DVDD1 PD20 4 mA J, B, G , G1 input p DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 PD20 4 mA J, B, G , G1 input p PD20 PD20 PD20 PD20 PD20 4 mA J, B, G , G1 input p 4 mA J, B, G , G1 input p 4 mA J, B, G , G1 input p PD20 PD20 PD20 PD20 PD20 PD20 4 mA J, B, G , G1 input p 4 mA J, B, G , G1 input p DVDD1 4 mA J, B, G , G1 input p DVDD1 M15 5 GPIO2 SPI.CLK PD20 4 mA J, B, G , G1 input p DVDD1 I = Input, O = Output, Z = High-Impedance 'regx' denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x PD20 = 20-A internal pulldown, PD100 = 100-A pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = Fail-safe LVCMOS input/output G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/output G3 = Terminal may be gated by BFAIL and PWRON_RESET D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Fail-safe LVCMOS input and Standard LVCMOS output J = Boundary-scannable terminal F = analog oscillator terminals # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low || UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module. 28 SPRS197D August 2002 - Revised August 2004 Introduction Table 2-3. Terminal Characteristics and Multiplexing (Continued) GZG BALL R19 9 R18 8 GDY BALL M17 M16 6 SIGNAL NAME GPIO1 UART3.RTS GPIO0 SPI.RDY USB.VBUS T20 0 T19 9 L13 3 N15 5 MPUIO5 LOW_PWR MPUIO4 EXT_DMA_REQ1 LED2 N15 5 U19 T18 V20 U8 U18 N17 M14 P15 N14 P17 MPUIO2 EXT_DMA_REQ0 MPUIO1 I2C.SCL I2C.SDA UWIRE.SDI UART3.DSR UART1.DSR MCBSP3.DR W21 P16 6 UWIRE.SDO UART3.DTR UART1.DTR MCBSP3.DX V19 9 N14 M13 3 R16 6 UWIRE.SCLK KB.C[7] pin forced to high-z UWIRE.CS0 MCBSP3.CLKX P15 5 L12 pin forced to high-z UWIRE.CS3 KB.C[6] W19 AA20 V18 Y19 AA19 V17 TYPE I/O/Z O I/O/Z I I I/O/Z O I/O/Z I O I/O/Z I I/O/Z I/O/Z I/O/Z I I I I O O O O O O Z O I/O/Z Z O O I I I I O I MUX CTRL SETTING reg7[8:6] = 000 reg7[8:6] = 001 reg7[11:9] = 000 reg7[11:9] = 001 reg7[11:9] = 010 reg7[14:12] = 000 reg7[14:12] = 001 reg7[17:15] = 000 reg7[17:15] = 001 reg7[17:15] = 010 reg7[20:18] = 000 reg7[20:18] = 001 NA NA NA reg8[2:0] = 000 reg8[2:0] = 001 reg8[2:0] = 010 reg8[2:0] = 011 reg8[5:3] = 000 reg8[5:3] = 001 reg8[5:3] = 010 reg8[5:3] = 011 reg8[8:6] = 000 reg8[8:6] = 001 reg8[11:9] = 000 reg8[11:9] = 001 reg8[11:9] = 010 reg8[14:12] = 000 reg8[14:12] = 001 reg8[14:12] = 010 NA NA NA NA NA NA DESELECTED INPUT STATE NA NA NA NA 0 NA NA NA NA NA NA NA NA NA NA NA 1 1 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA PU/ PD PD20 PD20 PD20 PD20 PD20 BUFFER STRENGTH 4 mA 4 mA OTHER J, B, G , G1 J, B, G , G1 RESET STATE# input p input p SUPPLY DVDD1 DVDD1 4 mA 4 mA J, B, G , G1 J, B, G , G1 input p input p DVDD1 DVDD1 PD20 4 mA 4 mA 6 mA 6 mA J, B, G , G1 B, J J, D, H1 J, D, H1 B, J , input p input Z Z input p DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 PD20 PD20 PD20 PD20 4 mA 4 mA J, A, G , G1 0 DVDD1 4 mA 4 mA J, A, G , G1 J, A 0 Z DVDD1 DVDD1 4 mA J, A Z DVDD1 R14 T15 T16 U17 U16 R13 BFAIL/EXT_FIQ CLK32K_CTRL CONF TDI TDO TMS J, B J, B PD10 0 PD20 4 mA PD20 A B A B input input input input 0 input DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 I = Input, O = Output, Z = High-Impedance 'regx' denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x PD20 = 20-A internal pulldown, PD100 = 100-A pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = Fail-safe LVCMOS input/output G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/output G3 = Terminal may be gated by BFAIL and PWRON_RESET D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Fail-safe LVCMOS input and Standard LVCMOS output J = Boundary-scannable terminal F = analog oscillator terminals # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low || UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module. August 2002 - Revised August 2004 SPRS197D 29 Introduction Table 2-3. Terminal Characteristics and Multiplexing (Continued) GZG BALL W18 Y18 V16 W17 Y17 AA17 GDY BALL T14 U15 R17 T13 U14 R12 SIGNAL NAME TCK TRST EMU0 EMU1 STAT_VAL/WKUP MPU_BOOT MCBSP3_DR USB1_SUSP P14 U3 U13 RST_HOST_OUT MCBSP3.DX USB1.SE0 W16 6 P14 pin forced to high-z MCBSP3.CLKX USB1.TXEN V15 W15 AA15 5 R14 V14 Y14 W14 P12 M11 U U12 M10 R11 P13 3 N12 MPU_RST RST_OUT pin forced to drive low UART1.RTS UART1.CTS UART1.RX pin forced to drive low UART1.TX MCSI1.DOUT USB1.TXD UART1.TX R13 3 L10 0 BCLKREQ UART3.CTS UART1.DSR Y13 3 P11 BCLK UART3.RTS UART1.DTR V13 3 TYPE I I I/O/Z I/O/Z I I I O O O O Z I/O/Z O I O O O I I O O O O O I I I O O O I/O/Z I MUX CTRL SETTING NA NA NA NA NA reg8[29:27] = 000 reg8[29:27] = 001 reg8[29:27] = 010 reg9[2:0] = 000 reg9[2:0] = 001 reg9[2:0] = 010 reg9[5:3] = 000 reg9[5:3] = 001 reg9[5:3] = 010 NA NA reg9[14:12] = 000 reg9[14:12] = 001 NA NA reg9[23:21] = 000 reg9[23:21] = 001 reg9[26:24] = 000 reg9[26:24] = 001 reg9[26:24] = 001|| reg9[29:27] = 000 reg9[29:27] = 001 reg9[29:27] = 010 regA[2:0] = 000 regA[2:0] = 001 regA[2:0] = 010 regA[5:3] = 000 regA[5:3] = 001 DESELECTED INPUT STATE NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 0 0 1 NA NA NA 0 NA PU/ PD PD20 PD10 0 PU10 0 PU10 0 PD20 PD20 BUFFER STRENGTH OTHER B B RESET STATE# input input Z Z input input p SUPPLY DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 2 mA 2 mA B B A 4 mA J, B 4 mA J, A, G , G1 0 DVDD1 PD20 PD20 4 mA J, A, G , G1 Z DVDD1 J, B 4 mA 2 mA PD20 PD20 2 mA 2 mA J, A J, A, G , G1 J, B J, B J, A, G , G1 J, A, G , , G1, H1 input 0 0 input input 0 0 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 PD20 PD20 PD20 4 mA J, B input p DVDD1 J, A, G , G1 0 DVDD1 T11 MCSI1.SYNC USB1.VP PD20 PD20 2 mA J, B, G , G1 input p DVDD1 I = Input, O = Output, Z = High-Impedance 'regx' denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x PD20 = 20-A internal pulldown, PD100 = 100-A pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = Fail-safe LVCMOS input/output G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/output G3 = Terminal may be gated by BFAIL and PWRON_RESET D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Fail-safe LVCMOS input and Standard LVCMOS output J = Boundary-scannable terminal F = analog oscillator terminals # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low || UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module. 30 SPRS197D August 2002 - Revised August 2004 Introduction Table 2-3. Terminal Characteristics and Multiplexing (Continued) GZG BALL AA13 3 GDY BALL U U11 SIGNAL NAME MCSI1.CLK USB1.VM UART1.RX W13 3 R10 0 MCSI1.DIN USB1.RCV UART1.CTS Y12 N10 0 CLK32K_OUT MPUIO0 USB1.SPEED P13 W12 R12 W11 N9 T10 T9 R9 9 CLK32K_IN OSC32K_IN OSC32K_OUT MMC.DAT3 Reserved MPUIO6 V11 R11 W10 0 U10 U9 R8 8 MMC.CLK MMC.DAT0/SPI.DI MMC.DAT2 pin forced to hi-z MPUIO11 V10 0 M9 9 MMC.DAT1 Reserved MPUIO7 P11 Y10 0 AA9 9 W9 9 V9 9 Y9 R10 0 W8 Y8 TYPE I/O/Z I I I I I O I/O/Z O I - - I/O/Z NA I/O/Z O I/O/Z I/O/Z Z I/O/Z I/O/Z NA I/O/Z I/O/Z I/O/Z O I I O O I/O/Z I/O/Z O I O I/O/Z I/O/Z MUX CTRL SETTING regA[8:6] = 000 regA[8:6] = 001 regA[8:6] = 001|| regA[11:9] = 000 regA[11:9] = 001 regA[11:9] = 001|| regA[14:12] = 000 regA[14:12] = 001 regA[14:12] = 010 NA NA NA regD[14:12] = 000 regD[14:12] = 001 regD[14:12] = 010 NA NA regA[20:18] = 000 regA[20:18] = 001 regA[20:18] = 010 regA[26:24] = 000 regA[26:24] = 001 regA[26:24] = 010 NA regB[5:3] = 000 regB[5:3] = 001 regB[8:6] = 000 regB[8:6] = 001 regB[11:9] = 000 regB[11:9] = 001 regB[14:12] = 000 regB[14:12] = 001 NA regB[20:18] = 000 regB[20:18] = 001 NA NA DESELECTED INPUT STATE 0 0 0 NA 0 0 NA NA NA NA NA NA 1 NA NA NA NA 1 NA NA 1 NA NA NA 0 NA NA 0 NA NA 0 NA NA 0 NA NA NA PU/ PD PD20 PD20 PD20 PD20 PD20 PD20 BUFFER STRENGTH 2 mA OTHER J, B, G , G1 RESET STATE# input p SUPPLY DVDD1 J, B input p DVDD1 8 mA J, A LZ DVDD1 J, B F F PU20 PU20 4 mA PU20 PU20 PU20 PU20 PU20 PU10 0 PD20 PD20 PD20 4 mA PD20 PD20 4 mA PD20 PD20 PD20 4 mA 4 mA 4 mA J, A, G1 J, E J, E, G3 J, E, G3 4 mA J, A, G , G2 J, E 4 mA 4 mA J, B, G1 J, E J, B 4 mA J, B, G , G1 4 mA 4 mA J, A, G1 J, B, G1 J, B, G , G1 4 mA J, B, J B G1 input NA NA input p DVDD1 NA NA DVDD1 0 input input p DVDD1 DVDD1 DVDD1 input p DVDD1 U8 T8 8 P8 8 T7 R7 U7 N8 8 M8 U6 MMC.CMD/SPI.DO MCSI2.CLK USB2.SUSP MCSI2.DIN USB2.VP MCSI2.DOUT USB2.TXEN MCSI2.SYNC GPIO7 MCLK MCLKREQ EXT_MASTER_REQ input input p input p 0 input p 0 input p input input DVDD1 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 GPIO9 GPIO8 I = Input, O = Output, Z = High-Impedance 'regx' denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x PD20 = 20-A internal pulldown, PD100 = 100-A pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = Fail-safe LVCMOS input/output G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/output G3 = Terminal may be gated by BFAIL and PWRON_RESET D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Fail-safe LVCMOS input and Standard LVCMOS output J = Boundary-scannable terminal F = analog oscillator terminals # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low || UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module. August 2002 - Revised August 2004 SPRS197D 31 Introduction Table 2-3. Terminal Characteristics and Multiplexing (Continued) GZG BALL V8 P10 0 W7 V7 Y6 W6 6 AA5 5 R9 9 Y5 5 GDY BALL P7 R6 6 T6 T5 5 U5 P6 6 R5 5 M7 N6 6 SIGNAL NAME MPUIO3 MCBSP2.DR MCBSP2.DX MCBSP2.FSX MCBSP2.CLKR GPIO11 MCBSP2.CLKX MCBSP2.FSR GPIO12 MCBSP2.DX MCBSP2.DR UART2.RX USB2.VM UART2.CTS USB2.RCV GPIO7 W5 5 U U4 pin forced to drive low UART2.RTS USB2.SE0 MPUIO5 V6 6 R4 pin forced to drive low UART2.TX USB2.TXD Y4 W4 P9 R8 Y2 W3 V4 W2 W1 U4 TYPE I/O/Z I O I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z O I I I I I I/O/Z O O O I/O/Z O O O O O O I/O/Z I/O/Z - - O/Z O/Z O/Z O/Z MUX CTRL SETTING NA regC[2:0] = 000 regC[2:0] = 001 NA regC[8:6] = 000 regC[8:6] = 001 NA regC[14:12] = 000 regC[14:12] = 001 regC[17:15] = 000 regC[17:15] = 001 regC[20:18] = 000 regC[20:18] = 001 regC[23:21] = 000 regC[23:21] = 001 regC[23:21] = 010 regC[26:24] = 000 regC[26:24] = 001 regC[26:24] = 010 regC[26:24] = 011 regC[29:27] = 000 regC[29:27] = 001 regC[29:27] = 010 NA regD[5:3] = 000 regD[5:3] = 001 NA NA NA NA NA NA NA NA DESELECTED INPUT STATE NA NA NA 0 0 NA NA 0 NA NA NA 1 0 1 0 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA PU/ PD PD20 PD20 PD20 PD20 PD20 PD20 BUFFER STRENGTH 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA OTHER J, E, G1 J, B, G , G2 J, E, G2 J, E J, E, G2 J, E J, E, G , G2 J, B J, B J, B J, E RESET STATE# input input p input Z input Z 0 input p input p SUPPLY DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 PD20 PD20 PD20 PD20 PD20 PD20 4 mA 4 mA 4 mA J, E, G , G2 0 DVDD3 4 mA J, A, G , G2 0 DVDD3 T4 T3 3 P5 P4 R2 P3 R3 P2 T2 N3 UART2.BCLK USB.PUEN USB.CLKO USB.DP USB.DM OSC1_IN OSC1_OUT FLASH.WP FLASH.WE FLASH.RP FLASH.OE 4 mA 8 mA 18.3 mA 18.3 mA J, A, G2 J, B, G , G1 C C F F 0 0 Z Z NA NA 0 1 0 1 DVDD3 DVDD2 DVDD2 DVDD2 NA NA DVDD5 DVDD5 DVDD5 DVDD5 4 mA 4 mA 4 mA 4 mA A A A A I = Input, O = Output, Z = High-Impedance 'regx' denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x PD20 = 20-A internal pulldown, PD100 = 100-A pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = Fail-safe LVCMOS input/output G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/output G3 = Terminal may be gated by BFAIL and PWRON_RESET D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Fail-safe LVCMOS input and Standard LVCMOS output J = Boundary-scannable terminal F = analog oscillator terminals # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low || UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module. 32 SPRS197D August 2002 - Revised August 2004 Introduction Table 2-3. Terminal Characteristics and Multiplexing (Continued) GZG BALL V3 T4 U3 U1 P8 T3 T2 R4 R3 R2 P7 P4 P2 N7 N2 N4 N3 N8 M4 M3 M7 M8 L3 L4 L7 K3 K4 L8 J1 J3 J4 J2 K7 H3 H4 K8 G2 G3 G4 F3 J7 E3 F4 D2 E4 C1 D3 J8 H7 E5 GDY BALL U2 T1 N2 R1 M3 P1 N1 N4 M5 M4 M2 M1 L6 L4 K3 L5 K4 L1 K5 5 K1 J2 J1 J5 H1 J3 J4 H6 H5 H2 H4 H3 G2 G1 G5 G3 G4 E1 F2 F4 F3 F5 D2 E4 E3 C2 C1 G6 B1 C3 N11 SIGNAL NAME FLASH.D[15:0] TYPE I/O/Z MUX CTRL SETTING NA DESELECTED INPUT STATE NA PU/ PD BUFFER STRENGTH 4 mA OTHER E RESET STATE# 0 SUPPLY DVDD5 FLASH.CLK FLASH.CS3 FLASH.CS2 FLASH.BAA FLASH.CS1 FLASH.CS0 FLASH.BE[1:0] FLASH.ADV FLASH.A[24:1] O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z NA NA regD[8:6] = 000 regD[8:6] = 001 NA NA NA NA NA NA NA NA NA NA NA NA NA NA 8 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA E, G1, H2 A A A A A A A, G1 0 1 1 1 1 0 1 0 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 FLASH.RDY RSVD I NA NA NA NA NA B input NA DVDD5 NA I = Input, O = Output, Z = High-Impedance 'regx' denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x PD20 = 20-A internal pulldown, PD100 = 100-A pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = Fail-safe LVCMOS input/output G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/output G3 = Terminal may be gated by BFAIL and PWRON_RESET D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Fail-safe LVCMOS input and Standard LVCMOS output J = Boundary-scannable terminal F = analog oscillator terminals # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low || UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module. August 2002 - Revised August 2004 SPRS197D 33 Introduction 2.4 Signal Description Table 2-4 provides a description of the signals on OMAP5910. Many signals are available on multiple pins depending upon the software configuration of the pin multiplexing options. Ball numbers which are italicized indicate the default pin muxings at reset. Ball numbers for busses are listed from MSB to LSB (left to right, top to bottom). Table 2-4. Signal Description SIGNAL GZG BALL C3 A2 D4 GDY BALL A1 C4 A2 DESCRIPTION TYPE EMIFF SDRAM Interface SDRAM.WE SDRAM.RAS SDRAM.DQMU SDRAM write enable. SDRAM.WE is active (low) during writes, DCAB, and MRS commands to SDRAM memory. SDRAM row address strobe. SDRAM.RAS is active (low) during ACTV, DCAB, REFR, and MRS commands to SDRAM memory. SDRAM upper data mask. Active-low data mask for the upper byte of the SDRAM data bus (SDRAM.D[15:8]). The data mask outputs allow for both 16-bit-wide and 8-bit-wide accesses to SDRAM memories. SDRAM lower data mask. Active-low data mask for the lower byte of the SDRAM data bus (SDRAM.D[7:0]). The data mask outputs allow for both 16-bit-wide and 8-bit-wide accesses to SDRAM memories. SDRAM data bus. SDRAM.D[15:0] provides data exchange between the Traffic Controller and SDRAM memory. O/Z O/Z O/Z SDRAM.DQML B3 B2 O/Z SDRAM.D[15:0] D5, C4, B4, D6, C5, H8, C6, B6, D7, C7, D8, B8, G8, C8, G9, B9 D9 D4, C5, G8, B4, B5, C6, A3, E6, D6, A4, B6, F7, C7, B7, D7, A6 D7 I/O/Z SDRAM.CKE SDRAM clock enable. Active-high output which enables the SDRAM clock during normal operation; SDRAM.CKE is driven inactive to put the memory into low-power mode. SDRAM clock. Clock for synchronization SDRAM memory commands/accesses. To minimize voltage undershoot and overshoot effects, it is recommended to place a series resistor (typically ~33 ) close to the SDRAM.CLK driver pin. SDRAM.CLK can also be configured as an input to monitor skew control. SDRAM column address strobe. SDRAM.CAS is active (low) during reads, writes, and the REFR and MRS commands to SDRAM memory. SDRAM bank address bus. Provides the bank address to SDRAM memories. O/Z SDRAM.CLK C9 A7 I/O/Z SDRAM.CAS SDRAM.BA[1:0] H9 D10, C10 F8 C9, B8 O/Z O/Z I = Input, O = Output, Z = High-Impedance All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain a capability for independent measurement of core supply currents to facilitate power optimization experiments. See Sections 5.6.1 and 5.6.2 for special V SS considerations with oscillator circuits. 34 SPRS197D August 2002 - Revised August 2004 Introduction Table 2-4. Signal Description (Continued) SIGNAL GZG BALL G10, H10, C11, D11, G11, C12, D12, H11, C13, D13, G12, C14, B14 GDY BALL C8, B9, E9, A8, C10, F9, D9, A9, D10, C11, B10, A10, B11 DESCRIPTION TYPE EMIFF SDRAM Interface (Continued) SDRAM.A[12:0] SDRAM address bus. Provides row and column address information to the SDRAM memory as well as MRS command data. SDRAM.A[10] also serves as a control signal to define specific commands to SDRAM memory. O/Z EMIFS FLASH and Asynchronous Memory Interface FLASH.WP FLASH.WE FLASH.RP FLASH.OE FLASH.D[15:0] V4 W2 W1 U4 V3, T4, U3, U1, P8, T3, T2, R4, R3, R2, P7, P4, P2, N7, N2, N4 N3 N8 M4 M3 M7 M8, L3 L4 M4 R3 P2 T2 N3 U2, T1, N2, R1, M3, P1, N1, N4, M5, M4, M2, M1, L6, L4, K3, L5 K4 L1 K5 K1 J2 J1, J5 H1 K5 EMIFS byte enables. Active-low byte enable signals used to perform byte-wide accesses to memories or devices that support byte enables. EMIFS address valid. Active-low control signal used to indicate a valid address is present on the FLASH.A[24:1] bus. EMIFS burst advance acknowledge. Active-low control signal used with Advanced Micro Devices burst Flash. FLASH.BAA is multiplexed with FLASH.CS2. O/Z O/Z O/Z EMIFS write protect. Active-low output for hardware write protection feature on standard memory devices. EMIFS write enable. Active-low write enable output for Flash or SRAM memories or asynchronous devices. EMIFS power down or reset output (Intel flash devices) EMIFS output enable. Active-low output enable output for Flash or SRAM memories or asynchronous devices. EMIFS data bus. Bidirectional 16-bit data bus used to transfer read and write data during EMIFS accesses. O/Z O/Z O/Z O/Z I/O/Z FLASH.CLK FLASH.CS3 FLASH.CS2 FLASH.CS1 FLASH.CS0 FLASH.BE[1:0] FLASH.ADV FLASH.BAA EMIFS clock. Clock output that is active during synchronous modes of EMIFS operation for synchronous burst Flash memories. EMIFS chip selects. Active-low chip-select outputs that become active when the p p p appropriate address i d i dd is decoded i d d internal to the device. Each chip select decodes a l hdi E h hi l d d 32M-byte region of memory space space. O/Z O/Z / I = Input, O = Output, Z = High-Impedance All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain a capability for independent measurement of core supply currents to facilitate power optimization experiments. See Sections 5.6.1 and 5.6.2 for special V SS considerations with oscillator circuits. Intel is a registered trademark of Intel Corporation. Advanced Micro Devices is a trademark of Advanced Micro Devices, Inc. August 2002 - Revised August 2004 SPRS197D 35 Introduction Table 2-4. Signal Description (Continued) SIGNAL GZG BALL L7, K3, K4, L8, J1, J3, J4, J2, K7, H3, H4, K8, G2, G3, G4, F3, J7, E3, F4, D2, E4, C1, D3, J8 H7 GDY BALL J3, J4, H6, H5, H2, H4, H3, G2, G1, G5, G3, G4, E1, F2, F4, F3, F5, D2, E4, E3, C2, C1, G6, B1 C3 DESCRIPTION TYPE EMIFS FLASH and Asynchronous Memory Interface (Continued) FLASH.A[24:1] EMIFS address bus. Address output bus for all EMIFS accesses. FLASH.A[24:1] provides the upper 24 bits of a 25-bit byte address. The byte enables must be used to implement 8-bit accesses. O/Z FLASH.RDY EMIFS ready. Active-high ready input used to suspend the EMIFS interface when the external memory or asynchronous device is not ready to continue the current cycle. It is recommended that this pin should be pulled high externally and unused. See the OMAP5910 Dual-Core Processor Silicon Errata (literature number SPRZ016) for more details. LCD vertical sync output. LCD.VS is the frame clock which signals the start of a new frame of pixels to the LCD panel. In TFT mode, LCD.VS is the vertical synchronization signal. LCD horizontal sync. LCD.HS is the line clock which signals the end of a line of pixels to the LCD panel. In TFT mode, LCD.HS is the horizontal synchronization signal. LCD AC-bias. LCD.AC is used to signal the LCD to switch the polarity of the row and column power supplies to counteract charge buildup causing DC offset. In TFT mode, LCD.AC is used as the output enable to latch LCD pixel data using the pixel clock. LCD pixel clock output. Clock output provided to synchronize pixel data to the LCD panel. In passive mode, LCD.PCLK only transitions when LCD.P[15:0] is valid. In active mode, LCD.PCLK transitions continuously and LCD.AC is used as the output enable when LCD.P[15:0] is valid. I LCD Interface LCD.VS D14 D11 O LCD.HS H12 E11 O LCD.AC B15 A11 O LCD.PCLK C15 A12 O I = Input, O = Output, Z = High-Impedance All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain a capability for independent measurement of core supply currents to facilitate power optimization experiments. See Sections 5.6.1 and 5.6.2 for special V SS considerations with oscillator circuits. 36 SPRS197D August 2002 - Revised August 2004 Introduction Table 2-4. Signal Description (Continued) SIGNAL LCD Interface (Continued) LCD.P[15:0] D15, C16, A17, G13, B17, C17, D16, D17, C18, B19, A20, H13, G14, C19, B21, D18 V19, P15, C20, C21, E18, D19, D20, F18 M20, N21, N19, E19, E20, H14, F19, G18 G20 G21 Y6 W16, N14 H15, H18 W7 N18, P18, P19, P20 D12, C13, B12, F11, B13, E12, A13, C14, B14, A15, C15, B15, A16, D15, C16, B16 M13, L12, A17, D16, B17, E15, E16, C17 K16, K17, K14, D17, E17, F15, D14, D13 F13 G15 U5 P14, R16 F17, F16 T6 L15, K12, K13, L14 LCD pixel data bus. Pixel data is transferred on this output bus to LCD panel. O GZG BALL GDY BALL DESCRIPTION TYPE Keyboard Matrix Interface KB.C[7:0] Keyboard matrix column outputs. KB.Cx column outputs are used in conjunction with the KB.Rx row inputs to implement a 6x5 or 8x8 keyboard matrix. O KB.R[7:0] Keyboard matrix row inputs. KB.Rx row inputs are used in conjunction with the KB.Cx column outputs to implement a 6x5 or 8x8 keyboard matrix. I Multichannel Buffered Serial Ports (McBSPs) MCBSP1.CLKS MCBSP1.CLKX MCBSP2.CLKX MCBSP3.CLKX MCBSP1.FSX MCBSP2.FSX MCBSP3.FSX McBSP1 clock source. Provides external clock reference for use with transmitter or reciever. CLKS is only present on McBSP1. McBSP transmit clock. Serial shift clock reference for the transmitter. CLKX is present on all McBSPs. In the case of McBSP1 and McBSP3, the clock input to ll M BSP I h f M BSP1 d M BSP3 h l k i the McBSP receiver may also be provided on this terminal via an internal loop-back connection between the transmitter and receiver clocks. McBSP transmit frame sync. Frame synchronization for transmitter. FSX is p present on all McBSPs. In the case of McBSP1 and McBSP3, the frame sync , y input to the McBSP receiver may also be provided on this terminal via an internal i t t th M BSP i lb id d thi t i li it l loop-back connection between the transmitter and receiver frame syncs syncs. I I/O/Z // I/O/Z I = Input, O = Output, Z = High-Impedance All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain a capability for independent measurement of core supply currents to facilitate power optimization experiments. See Sections 5.6.1 and 5.6.2 for special V SS considerations with oscillator circuits. August 2002 - Revised August 2004 SPRS197D 37 Introduction Table 2-4. Signal Description (Continued) SIGNAL GZG BALL H18, H15 AA5, P10 P14, W21 V7 W6 H20 P10, AA5 AA17, U18 GDY BALL F16, F17 R5, R6 U13, P16 T5 P6 G16 R6, R5 R12, P17 McBSP2 receive clock. Serial shift clock reference for the receiver. CLKR is only present on McBSP2. McBSP2 receive frame sync. Frame synchronization for the receiver. FSR is only present on McBSP2. McBSP receive data. Serial receive data input. DR is present on all McBSPs. p p I/O/Z I/O/Z I DESCRIPTION TYPE Multichannel Buffered Serial Ports (McBSPs) (Continued) MCBSP1.DX MCBSP2.DX MCBSP3.DX MCBSP2.CLKR MCBSP2.FSR MCBSP1.DR MCBSP2.DR MCBSP3.DR Camera Interface CAM.EXCLK CAM.LCLK CAM.VS CAM.HS CAM.D[7:0] H19 J15 L18 L15 J18, J19, J14, K18, K19, K15, K14, L19 M19 G13 H15 J17 K15 G14, G12, H16, J15, G17, H17, H14, J16 J14 Camera interface external clock. Output clock used to provide a timing reference to a camera sensor. Camera interface line clock. Input clock to provide external timing reference from camera sensor logic. Camera interface vertical sync. Vertical synchronization input from external camera sensor. Camera interface horizontal sync. Horizontal synchronization input from external camera sensor. Camera interface data. Data input bus to receive image data from an external camera sensor. O I I I I McBSP transmit data. Serial transmit data output. DX is present on all McBSPs. O CAM.RSTZ ETM9 Trace Macro Interface ETM.CLK ETM.SYNC ETM.D[7:0] Camera interface reset. Reset output used to reset or Initialize external camera sensor logic. O J15 H19 J18, J19, J14, K18, K19, K15, K14, L19 H15 G13 G14, G12, H16, J15, G17, H17, H14, J16 ETM9 Trace Clock. Clock output for standard ETM9 test/debug equipment. ETM9 Trace Synchronization. Trace Sync output for standard ETM9 test/debug equipment. ETM9 Trace Packet data. Trace Packet outputs for standard ETM9 test/debug equipment. O O O I = Input, O = Output, Z = High-Impedance All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain a capability for independent measurement of core supply currents to facilitate power optimization experiments. See Sections 5.6.1 and 5.6.2 for special V SS considerations with oscillator circuits. 38 SPRS197D August 2002 - Revised August 2004 Introduction Table 2-4. Signal Description (Continued) SIGNAL GZG BALL L18, L15, M19 V19, J15 W21, H19 U18, J14 N14, J18 P15, J19 N20 GDY BALL J17, K15, J14 M13, H15 P16, G13 P17, H16 R16, G14 L12, G12 L16 DESCRIPTION TYPE ETM9 Trace Macro Interface (Continued) ETM.PSTAT[2:0] ETM9 Trace Pipe State 2-0. Pipeline status outputs for standard ETM9 test/debug equipment. O MICROWIRE Interface UWIRE.SCLK UWIRE.SDO UWIRE.SDI UWIRE.CS0 UWIRE.CS3 HDQ/1-Wire Interface HDQ HDQ/1-wire interface. HDQ optionally implements one of two serial protocols: HDQ or 1-Wire. Shared General-Purpose I/O. Each GPIO pin can be used by either the DSP core p / p y or the MPU core. Control of each GPIO pin between the two cores is selected by h C lf h ib h i l db the MPU via control registers Each GPIO pin may also be configured to cause an registers. interrupt to its respective core processor. GPIO5 and GPIO10 are not available on the OMAP5910 device. device I/O MICROWIRE serial clock. This pin drives a clock to a MICROWIRE device. The active edge is software configurable. MICROWIRE serial data out. Write data is transferred to a MICROWIRE device on this pin. MICROWIRE serial data in. Read data is transferred from a MICROWIRE device on this pin. MICROWIRE chip select 0. The CS0 output selects a single MICROWIRE device (configurable as active high or active low). MICROWIRE chip select 3. The CS3 output selects a single MICROWIRE device (configurable as active high or active low). O O I O O General-Purpose I/O (GPIO) and MPU I/O (MPUIO) GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO9 GPIO8 GPIO7 M20 N21 N19 N18, W6 N20, V7 W8 Y8 M15, Y5, V9 P19 P20 P18 M14 R19 R18 K16 K17 K14 L15, P6 L16, T5 M8 U6 L17, N6, R7 K13 L14 K12 M15 M17 M16 I/O/Z // GPIO6 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 I = Input, O = Output, Z = High-Impedance All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain a capability for independent measurement of core supply currents to facilitate power optimization experiments. See Sections 5.6.1 and 5.6.2 for special V SS considerations with oscillator circuits. August 2002 - Revised August 2004 SPRS197D 39 Introduction Table 2-4. Signal Description (Continued) SIGNAL GZG BALL L19 W10 V10 W11 T20, W5 T19 V8 N15 U19 Y12 M18 L14 GDY BALL J16 R8 M9 R9 L13, U4 N15 P7 N17 M14 N10 J13 H12 Pulse Width Tone output. The PWT output pin provides a modulated output for use with an external buzzer. Pulse Width Light output. The PWL output pin provides a pseudo-random modulated voltage output used for LCD or keypad backlighting. MMC/SD clock. Clock output to the MMC/SD card. MMC/SD command output. MMC/SD commands are transferred to/from this pin. SD card data bit 3. Data bit 3 used in 4-bit Secure Digital mode. SD card data bit 2. Data bit 2 used in 4-bit Secure Digital mode. SD card data bit 1. Data bit 1 used in 4 -bit Secure Digital mode. MMC/SD dat0 input. MMC.DAT0 functions as data bit 0 during MMC and Secure Digital operation. The pin functions as the data input in generic SPI mode. O O DESCRIPTION TYPE General-Purpose I/O (GPIO) and MPU I/O (MPUIO) (Continued) MPUIO12 MPUIO11 MPUIO7 MPUIO6 MPUIO5 MPUIO4 MPUIO3 MPUIO2 MPUIO1 MPUIO0 PWT PWL MPU General-Purpose I/O. MPUIO pins may only be used by the MPU core. p / p y y y MPUIO8, MPUIO9 AND MPUIO10 are not available on the OMAP5910 device device. MPUIO8 MPUIO9, I/O/Z // Pulse-Width Tone and Pulse-Width Light Interface Multimedia Card/Secure Digital Interface (MMC/SD) MMC.CLK MMC.CMD MMC.DAT3 MMC.DAT2 MMC.DAT1 MMC.DAT0 V11 P11 W11 W10, M15 V10 R11 U10 U8 R9 R8, L17 M9 U9 O I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I = Input, O = Output, Z = High-Impedance All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain a capability for independent measurement of core supply currents to facilitate power optimization experiments. See Sections 5.6.1 and 5.6.2 for special V SS considerations with oscillator circuits. 40 SPRS197D August 2002 - Revised August 2004 Introduction Table 2-4. Signal Description (Continued) SIGNAL GZG BALL Y14 V6, M18 M18, K18 V14 R9, L14 L14, K19 R14 Y5, L15 R13, K15 AA15 W5, M19 Y13, R19, K14 W21, Y13 W21 U18, R13 U18 Y4 GDY BALL P13 R4, J13 J13, J15 R11 M7, H12 H12, G17 M10 N6, K15 L10, H17 U12 U4, J14 P11, M17, H14 P16, P11 P16 P17, L10 P17 T4 UART baud clock output. A clock of 16x of the UART2 baud rate is driven onto this pin. This feature is only implemented on UART2. I2C serial clock. I2C.SCL provides the timing reference for I2C transfers. I2C serial data. I2C.SDA provides control and data for I2C transfers. O UART data-set-ready. DSR is only present on UART1 and UART3. I UART data-terminal-ready. DTR is only present on UART1 and UART3. O UART request-to-send. RTS is present on all UARTs. On UART3 in IrDA mode, q p , this pin is SD_MODE. hi i i SD MODE O UART clear-to-send. CTS is present on all UARTs. p I UART receive. Receive data input. RX is p p present on all UARTs. On UART3, the , RX pin implements the RXIR function during SIR mode operation. ii l h f i di d i I DESCRIPTION TYPE Universal Asynchronous Receiver/Transmitter Interfaces UART1.TX UART2.TX UART3.TX UART1.RX UART2.RX UART3.RX UART1.CTS UART2.CTS UART3.CTS UART1.RTS UART2.RTS UART3.RTS UART transmit. Transmit data output. TX is p p present on all UARTs. On UART3, the , TX pin implements the TXIR function during SIR mode operation. ii l h f i di d i O UART1.DTR UART3.DTR UART1.DSR UART3.DSR UART2.BCLK Inter-Integrated Circuit Master and Slave Interface I2C.SCL I2C.SDA LED1 LED2 T18 V20 P18 T19 P15 N14 K12 N15 I/O/Z I/O/Z O O LED Pulse Generator Interface LED Pulse Generator output 1. LED1 produces a static or pulsing output used to drive an external LED indicator. LED Pulse Generator output 2. LED2 produces a static or pulsing output used to drive an external LED indicator. MCSI clock. Multichannel Serial Interface clock reference. The clock can be driven in i master mode or an external clock may be driven on this signal in slave mode. d ll k b di hi i li l d MCSI sync. Multichannel Serial Interface frame synchronization signal. The frame sync can be driven in master mode or an external clock may be driven on this signal in slave mode. MCSIx.SYNC may be configured as an active-low or active-high sync. Multichannel Serial Interfaces (MCSIs) MCSI1.CLK MCSI2.CLK MCSI1.SYNC MCSI2.SYNC AA13 Y10 V13 V9 U11 T8 T11 R7 I/O/Z // I/O/Z I = Input, O = Output, Z = High-Impedance All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain a capability for independent measurement of core supply currents to facilitate power optimization experiments. See Sections 5.6.1 and 5.6.2 for special V SS considerations with oscillator circuits. August 2002 - Revised August 2004 SPRS197D 41 Introduction Table 2-4. Signal Description (Continued) SIGNAL GZG BALL W13 AA9 W14 W9 P9 GDY BALL R10 P8 N12 T7 P5 USB internal transceiver D+. The positive side of the integrated USB transceiver's differential bus. A series resistor of 27 (5% tolerance) is required on the USB.DP pin. USB internal transceiver D-. The negative side of the integrated USB transceiver's differential bus. A series resistor of 27 (5% tolerance) is required on the USB.DM pin. USB transmit enable. Driven active (low) when the USB host or Function ( ) peripheral is driving data onto the USB bus via the TXD output. i h li di i d h b ih USB transmit data. Single-ended logic output used to transmit data to the transmit input of an external USB transceiver. USBx.TXD may also be used for transceiverless connection between OMAP5910 and another transceiverless USB device. USB vplus data. Single-ended input used to monitor the logical state of the D+ line of the USB bus USBx VP should be driven by an external USB transceiver based bus. USBx.VP on the state of D+. USB vminus data. Single-ended input used to monitor the logical state of the D- line of the USB bus USBx VM should be driven by an external USB transceiver bus. USBx.VM based on the state of D-. USB receive data. Single-ended logic input used to receive data from the receive output of an external USB transceiver. USBx.RCV may also be used for transceiverless connection between OMAP5910 and another transceiverless USB device. USB bus segment suspend control. Active-high output indicates detection of IDLE condition on the USB bus for greater than 5 ms USBx SUSP is implemented on ms. USBx.SUSP both USB ports 1 and 2. USB single-ended zero. Active-high output indicates detection of the single-ended g g p g zero state on the USB bus. USBx.SE0 is implemented for both USB ports 1 and 2. h b USB SE i i l df b h d USB 1 bus segment speed control. Static control output used by the external transceiver to determine whether USB port 1 is operating in full-speed or low-speed mode. USB1.SPEED is only implemented on USB port 1. I/O/Z MCSI data out. Multichannel Serial Interface data output pin. pp O DESCRIPTION TYPE Multichannel Serial Interfaces (MCSIs) (Continued) MCSI1.DIN MCSI2.DIN MCSI1.DOUT MCSI2.DOUT USB.DP MCSI data in. Multichannel Serial Interface data input pin. pp I USB (Integrated Transceiver Interface, can be used with Host or Function) USB.DM R8 P4 I/O/Z USB Pin Group 1 and 2 (Utilizing External Transceivers, can be used with Host or Function) USB1.TXEN USB2.TXEN USB1.TXD USB2.TXD USB1.VP USB2.VP USB1.VM USB2.VM USB1.RCV USB2.RCV USB1.SUSP USB2.SUSP USB1.SE0 USB2.SE0 USB1.SPEED W16 W9 W14 V6 V13 AA9 AA13 R9 W13 Y5 AA17 Y10 P14 W5 Y12 P14 T7 N12 R4 T11 P8 U11 M7 R10 N6 R12 T8 U13 U4 N10 O O I I I O O O I = Input, O = Output, Z = High-Impedance All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain a capability for independent measurement of core supply currents to facilitate power optimization experiments. See Sections 5.6.1 and 5.6.2 for special V SS considerations with oscillator circuits. 42 SPRS197D August 2002 - Revised August 2004 Introduction Table 2-4. Signal Description (Continued) SIGNAL USB Miscellaneous Signals USB.CLKO USB.PUEN W4 W4 T3 T3 USB clock output. 6-MHz divided clock output of the internal USB DPLL provided for reference. Common for all USB host and Function peripherals. USB pullup enable. Control output used in conjunction with an external pullup resistor to implement USB device connect and disconnect via software. USB.PUEN is used with the USB Function peripheral. USB voltage bus enable. USB.VBUS is used to provide a logic-high voltage level which may be used to enable pullup resistors on the USB bus to indicate connection or disconnection status of the OMAP5910 device as a USB Function device. IEEE Standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on the test access port (TAP) of input signals TDI and TMS are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal TDO occur on the falling edge of TCK. IEEE Standard 1149.1 test data input. TDI is clocked into the selected register (instruction or data) on the rising edge of TCK. IEEE Standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. IEEE Standard 1149.1 test mode select. This serial control input is clocked into the TAP controller on the rising edge of TCK. IEEE Standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the operations of the device. If TRST is not connected, or driven low, the device operates in its functional mode, and the IEEE standard 1149.1 signals are ignored. Emulation pin 0. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. Emulation pin 1. When TRST is driven high, EMU1 is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. O O GZG BALL GDY BALL DESCRIPTION TYPE USB.VBUS R18 M16 I JTAG/Emulation Interface TCK W18 T14 I TDI TDO Y19 AA19 U17 U16 I O TMS TRST V17 Y18 R13 U15 I I EMU0 V16 R17 I/O EMU1 W17 T13 I/O Device Clock Pins CLK32K_IN CLK32K_OUT CLK32K_CTRL P13 Y12 AA20 N9 N10 T15 32-kHz clock input. Digital CMOS 32-kHz clock input driven by an external 32-kHz oscillator if the internal 32-kHz oscillator is not used. 32-kHz clock output. Clock output reflecting the internal 32-kHz clock. 32-kHz clock selection control input. CLK32K_CTRL selects whether or not the internal 32-kHz oscillator is used or if the 32-kHz clock is to be provided externally via the CLK32K_IN input. If CLK32K_CTRL is high, the 32-kHz internal oscillator is used; if CLK32K_CTRL is low, the CMOS input CLK32K_IN is used as a 32-kHz clock source. 32-kHz crystal XI connection. Analog clock input to 32-kHz oscillator for use with external crystal. 32-kHz crystal XO connection. Analog output from 32-kHz oscillator for use with external crystal. Base crystal XI connection. Analog input to base oscillator for use with external crystal or to be driven by external 12- or 13-MHz oscillator. I O I OSC32K_IN OSC32K_OUT OSC1_IN W12 R12 Y2 T10 T9 R2 analog analog analog I = Input, O = Output, Z = High-Impedance All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain a capability for independent measurement of core supply currents to facilitate power optimization experiments. See Sections 5.6.1 and 5.6.2 for special V SS considerations with oscillator circuits. August 2002 - Revised August 2004 SPRS197D 43 Introduction Table 2-4. Signal Description (Continued) SIGNAL GZG BALL W3 Y9 GDY BALL P3 U7 DESCRIPTION TYPE Device Clock Pins (Continued) OSC1_OUT MCLK Base crystal XO connection. Analog output from base oscillator for use with external 12- or 13-MHz crystal. M-Clock. General-purpose clock output which may be configured to run at 12 MHz or 48 MHz. MCLK may be configured to drive constantly or only when the MCLKREQ signal is asserted active high. B-Clock. General purpose clock output which may be configured to run at 12 MHz. BCLK may be configured to drive constantly or only when the BCLKREQ signal is asserted active high. M-Clock Request. Active high request input which allows an external device to request that MCLK be driven. B-Clock Request. Active high request input which allows an external device to request that BCLK be driven. analog O BCLK Y13 P11 O MCLKREQ BCLKREQ Reset Logic Pins PWRON_RESET MPU_RST RST_OUT R10 R13 N8 L10 I I G19 V15 W15 F14 P12 M11 Reset input to device. Active-low asynchronous reset input resets the entire OMAP5910 device. MPU reset input. Active-low asynchronous reset input resets the MPU core. Reset output. Active-low output is asserted when MPUST is active (after synchronization.) I I O Interrupts and Miscellaneous Control and Configuration Pins MPU_BOOT AA17 R12 MPU boot mode. When MPU_BOOT is low, the MPU boots from chip select 0 of the EMIFS (Flash) interface. When MPU_BOOT is high, the MPU boots from chip select 3 of EMIFS. DMA request external observation output. IRQ external observation output. External DMA requests. EXT_DMA_REQ0 and EXT_DMA_REQ1 provide two DMA request inputs which external devices may use to trigger System DMA transfers. The System DMA must be configured in software to respond to these external requests. Battery power failure and external FIQ interrupt input. BFAIL/EXT_FIQ may be used to gate certain input pins when battery power is low or failing. The pins which may be gated are configured via software. This pin can also optionally be used as an external FIQ interrupt source to the MPU. The function of this pin is configurable via software. External master request. If the 12-MHz clock is provided by an external device instead of using the on-chip oscillator, a high level on this output indicates to the external device that the clock must be driven. A low level indicates that the OMAP5910 device is in sleep mode and the 12-MHz clock is not necessary. Low-power request output. This active-high output indicates that the OMAP5910 device is in a low-power sleep mode. During reset and functional modes, LOW_PWR is driven low. This signal can be used to indicate a low-power state to external power management devices in a system or it can be used as a chip select to external SDRAM memory to minimize current consumption while the SDRAM is in self-refresh and the OMAP5910 device is in sleep mode. Configuration input. CONF selects reserved factory test modes. CONF should always be pulled low during device operation. I DMA_REQ_OBS IRQ_OBS EXT_DMA_REQ1 EXT_DMA_REQ0 BFAIL/EXT_FIQ L14 M18 T19 N15 W19 H12 J13 N15 N17 R14 O O I I EXT_MASTER_REQ R10 N8 O LOW_PWR T20 L13 O CONF V18 T16 I I = Input, O = Output, Z = High-Impedance All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain a capability for independent measurement of core supply currents to facilitate power optimization experiments. See Sections 5.6.1 and 5.6.2 for special V SS considerations with oscillator circuits. 44 SPRS197D August 2002 - Revised August 2004 Introduction Table 2-4. Signal Description (Continued) SIGNAL GZG BALL GDY BALL DESCRIPTION TYPE Interrupts and Miscellaneous Control and Configuration Pins (Continued) STAT_VAL/WKUP Y17 U14 Static Valid / Chip wake-up input. STAT_VAL/WKUP is also sampled at reset to select the MMC/SD port. If the MMC/SD peripheral is to be used, this pin must be pulled high during reset. It is recommended that this pin be pulled high during reset regardless of whether or not MMC/SD will be used. Reset Host output. A software controllable Reset or Shutdown output to an external device. Reserved pin. This pin must be left unconnected. I RST_HOST_OUT RSVD Power Supplies VSS P14 E5 U13 N11 O - A11, A13, A21, B1, B2, B5, B7, B16, B18, E2, F20, G1, J20, K2, K20, N1, R21, U2, U20, V5, V12, W20, Y3, Y15, AA1, AA7, AA21 A9, F2, P12, Y20 A3 Y1, AA3 B13, B20, J21, R20 M2 G9, H9, N5, H8, G11, M6, L11, K8, J12, J9, G7, E5, J7, J8, J6, J10, K10, H10, F12, L7, F6, L9, K9, M12, E13, J11, N13 E8, E2, T17, P10 B3 K7, L8 F10, G10, H11, K11 K2 Ground. Common ground return for all core and I/O voltage supplies. power CVDD Core supply voltage. Supplies power to OMAP5910 core logic and low-voltage sections of I/O. power CVDD1 CVDD2 CVDD3 Core Supply Voltage 1. Supplies power to the on-chip shared SRAM memory (192k-Bytes). Core Supply Voltage 2. Supplies power to the MPU subsystem logic and memory. Core Supply Voltage 3. Supplies power to the DSP subsystem logic and memory. power power power CVDD4 Core Supply Voltage 4. Supplies power to the DPLL which provides internal clocks to the core and peripherals (excluding USB peripherals). NOTE: The voltage to this supply pin should be kept as clean as possible to maximize performance. power I = Input, O = Output, Z = High-Impedance All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain a capability for independent measurement of core supply currents to facilitate power optimization experiments. See Sections 5.6.1 and 5.6.2 for special V SS considerations with oscillator circuits. August 2002 - Revised August 2004 SPRS197D 45 Introduction Table 2-4. Signal Description (Continued) SIGNAL Power Supplies (Continued) CVDDA Y21 R15 Analog supply voltage. Supplies power to ULPD DPLL which provides an internal clock to the USB peripherals. NOTE: The voltage to this supply pin should be kept as clean as possible to maximize performance. I/O Supply Voltage 1. Supplies power to the majority of peripheral I/O buffers. DVDD1 may be connected in common with the other DVDD supplies if the same operating voltage is desired. power GZG BALL GDY BALL DESCRIPTION TYPE DVDD1 A15, A19, E21, L21, U21, AA11, Y16 AA2 C12, A14, E14, H13, N16, P9, T12 U3 power DVDD2 I/O Supply Voltage 2. Supplies power to the internal USB transceiver buffers. DVDD2 may optionally be used for USB connect and disconnect detection by connecting DVDD2 to the power from the USB bus in the system. DVDD2 may be connected in common with the other DVDD supplies if the same operating voltage is desired. I/O Supply Voltage 3. Supplies power to the MCSI2 and McBSP2 peripheral I/O buffers as well as GPIO[9:8] I/O buffers. The DVDD3 supply may operate within a high-voltage or low-voltage range (see Section 5.2 for operating conditions). DVDD3 may be connected in common with the other DVDD supplies if the same operating voltage is desired. I/O Supply Voltage 4. Supplies power to the SDRAM interface I/O buffers. The DVDD4 supply may operate within a high-voltage or low-voltage range (see Section 5.2 for operating conditions). DVDD4 may be connected in common with the other DVDD supplies if the same operating voltage is desired. I/O Supply Voltage 5. Supplies power to the FLASH interface I/O buffers. The DVDD5 supply may operate within a high-voltage or low-voltage range (see Section 5.2 for operating conditions). DVDD5 may be connected in common with the other DVDD supplies if the same operating voltage is desired. power DVDD3 Y7 N7 power DVDD4 A1, A5, A7, B10, B12 C2, E1, H2, L1, P3, R1, V2 D3, D5, A5, D8, E10 H7, D1, F1, K6, L2, L3, U1 power DVDD5 power I = Input, O = Output, Z = High-Impedance All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain a capability for independent measurement of core supply currents to facilitate power optimization experiments. See Sections 5.6.1 and 5.6.2 for special V SS considerations with oscillator circuits. 46 SPRS197D August 2002 - Revised August 2004 3 OMAP5910 (289-Ball Package) 16 Timers (3) Watchdog Timer Level 1/2 Interrupt Handlers DSP Public Peripherals McBSP1 16 MCSI1 MCSI2 DSP Public (Shared) Peripheral Bus McBSP3 DSP Private Peripherals DSP Private Peripheral Bus 32 DSP MMU August 2002 - Revised August 2004 TMS320C55x DSP (Instruction Cache, SARAM, DARAM, DMA, H/W Accelerators) 16 32 MPU Interface MPU Bus 32 32 MPU/DSP Shared Peripherals Mailboxes GPIO I/F UART1, UART2, UART3 32 MPU 32 System DMA Controller 32 Bridge MPU Public Peripheral Bus Peripheral MPU Public Peripherals McBSP2 USB Function USB Host I M I F 32 32 MPU Private Peripheral Bus 32 Local Bus I/F and MMU I2 C I/F MICROWIRE I/F Functional Overview Flash and SRAM Memories 16 E M I F S 32 32 SDRAM Memories 16 Memory Interface Traffic Controller (TC) E M I F F 32 SRAM 192K Bytes 32 MPU Core (TI925T) (Instruction Cache, Data Cache, MMUs) LCD I/F ETM9 16 The following functional overview is based on the block diagram in Figure 3-1. Figure 3-1. OMAP5910 Functional Block Diagram MPU Private Peripherals Clock/Reset/Power Management OSC OSC Timers (3) Watchdog Timer Level 1/2 Interrupt Handlers Configuration Registers 12 MHz 32 kHz Clock Reset or 13 MHz External Clock Requests Camera I/F MPUIO HDQ/1-Wire I/F PWT I/F PWL I/F Keyboard I/F MMC/SD LPG x2 FAC RTC 32-kHz Timer JTAG/ Emulation I/F Functional Overview SPRS197D ETM9 pins are shared with the Camera Interface. 47 Functional Overview 3.1 Functional Block Diagram Features The OMAP5910 device includes the following functional blocks: * ARM9TDMI-based MPU core - - - - * - - - - - - * * 16K-byte instruction cache and 8K-byte data cache Memory Management Units (MMUs) for Instruction and Data Two 64-entry Translation Look-Aside Buffers (TLBs) for MMUs 17-word write buffer 48K-word single-access RAM (SARAM) (96K bytes) 32K-word dual-access RAM (DARAM) (64K bytes) 16K-word ROM (32K bytes) 24K-byte instruction cache Six-channel DMA controller Hardware Accelerators for DCT, iDCT, pixel interpolation, and motion estimation C55x DSP subsystem Nine-channel system DMA controller Traffic controller providing shared access to three memory interfaces: - - - EMIFF External Memory Interface providing 16-bit interface to 64M bytes of standard SDRAM EMIFS External Memory Interface providing 16-bit interface to 128M bytes of Flash, ROM, or asynchronous memories Internal Memory Interface (IMIF) providing 32-bit interface to 192K bytes of internal SRAM * * * * DSP Memory Management Unit (MMU) configured by the MPU MPU Interface (MPUI) allowing MPU and System DMA to access DSP subsystem memory and DSP public peripherals Local Bus Interface (with MMU) allowing USB host peripheral direct access to system memories. DSP Private Peripherals (accessible only by the DSP) - - - Three 32-bit general-purpose timers Watchdog timer Level 1/Level 2 interrupt handlers Two Multichannel Buffered Serial Ports (McBSPs) Two Multichannel Serial Interfaces (MCSIs) ideal for voice data Three 32-bit general-purpose timers Watchdog Timer Level 1/Level 2 interrupt handlers Configuration Registers for pin-multiplexing and other device-level configurations LCD controller supporting monochrome panels (STN) and color panels (STN or TFT) * DSP Public Peripherals (accessible by the DSP, DSP DMA, and the MPU via the MPU interface) - - * MPU Private Peripherals (accessible only by the MPU) - - - - - 48 SPRS197D August 2002 - Revised August 2004 Functional Overview * MPU Public Peripherals (accessible by the MPU and the System DMA) - - - - - - - - - - - - - - - - - Multichannel Buffered Serial Port (McBSP) USB Function interface (optional internal transceiver shared with USB Host interface) USB Host interface with up to three ports (optional internal transceiver shared with USB Function interface) One integrated USB transceiver for either host or Function Inter-Integrated Circuit (I2C) Multi-mode master and slave interface MICROWIRE serial interface Camera interface providing connectivity to CMOS image sensors Up to ten MPU general-purpose I/Os (MPUIOs) 32-kHz timer for use with MPU OS Pulse-Width Tone (PWT) module for tone generation Pulse-Width Light (PWL) module for LCD backlight control Keyboard interface (6 x 5 or 8 x 8 matrix) Multimedia Card or Secure Digital interface (MMC/SD) Two LED Pulse Generator modules (LPG) Real-Time Clock module (RTC) HDQ or 1-Wire Master interface for serial communication to battery management devices Frame Adjustment Counter (FAC) Four Mailboxes for interprocessor communications Up to 14 General-Purpose I/O pins with interrupt capability to either processor Three UARTs (UART3 has SIR mode for IrDA functionality) Configurable Digital Phase-Locked Loop (DPLL) providing clocks to MPU, DSP, and TC Dedicated DPLL with a 12 MHz input clock, or dedicated APLL with a 13 MHz input clock providing clocking to USB peripherals Integrated base (12- or 13-MHz) and 32-kHz oscillators utilizing external crystals Reset, clocking and idle/sleep controls for power management * MPU/DSP Shared Peripherals (Controlling processor is selected by the MPU) - - - * Clock/Reset/Power Management modules - - - - * JTAG and ETM9 interfaces for emulation and debug August 2002 - Revised August 2004 SPRS197D 49 Functional Overview 3.2 MPU Memory Maps The MPU has a unified address space. Therefore, the internal and external memories for program and data as well as peripheral registers and configuration registers are all accessed within the same address space. The MPU space is always addressed using byte addressing. Table 3-1 provides a high level illustration of the entire MPU addressable space. Further detail regarding the peripheral and configuration registers is provided in Sections 3.2.2, 3.15, and 3.17. Table 3-1. OMAP5910 MPU Global Memory Map BYTE ADDRESS RANGE 0x0000 0000 - 0x01FF FFFF 0x0200 0000 - 0x03FF FFFF 0x0400 0000 - 0x05FF FFFF 0x0600 0000 - 0x07FF FFFF 0x0800 0000 - 0x09FF FFFF 0x0A00 0000 - 0x0BFF FFFF 0x0C00 0000 - 0x0DFF FFFF 0x0E00 0000 - 0x0FFF FFFF 0x1000 0000 - 0x13FF FFFF 0x1400 0000 - 0x1FFF FFFF 0x2000 0000 - 0x2002 FFFF 0x2003 0000 - 0x2FFF FFFF 0x3000 0000 - 0x5FFF FFFF 0x6000 0000 - 0xDFFF FFFF DSP public memory space 0xE000 0000 - 0xE0FF FFFF (accessible via MPUI) 16M bytes 0xE100 0000 - 0xEFFF FFFF 0xF000 0000 - 0xFFFA FFFF 0xFFFB 0000 - 0xFFFB FFFF 0xFFFC 0000 - 0xFFFC FFFF 0xFFFD 0000 - 0xFFFE FFFF 0xFFFF 0000 - 0xFFFF FFFF MPU public peripherals MPU/DSP shared peripherals MPU private peripherals Reserved DSP public peripherals (accessible via MPUI) Reserved Local Bus space for USB Host Reserved IMIF Internal SRAM 192K bytes Reserved Reserved Reserved EMIFF (SDRAM) 64M bytes Reserved EMIFS (Flash CS3) 32M bytes Reserved EMIFS (Flash CS2) 32M bytes Reserved EMIFS (Flash CS1) 32M bytes ON-CHIP EXTERNAL INTERFACE EMIFS (Flash CS0) 32M bytes 3.2.1 MPU Global Memory Map Some peripherals within this memory region are actually shared peripherals (UART 1,2,3). 50 SPRS197D August 2002 - Revised August 2004 Functional Overview 3.2.2 MPU Subsystem Registers Memory Map The MPU accesses peripheral and configuration registers in the same way that internal and external memory is accessed. The following tables specify the MPU base addresses where each set of registers is accessed. All accesses to these registers must utilize the appropriate access width (8-, 16-, or 32-bit-wide accesses) as indicated in the tables. Accessing registers with the incorrect access width cause unexpected results including a TI Peripheral Bus (TIPB) bus error and associated TIPB interrupt. Refer to Sections 3.15, 3.16, and 3.17 for more detail about each of these register sets including individual register addresses, register names, descriptions, supported access types (read, write or read/write) and reset values. Table 3-2. MPU Private Peripheral Registers MPU BASE ADDRESS 0xFFFE 0000 0xFFFE C000 0xFFFE C500 0xFFFE C600 0xFFFE C700 0xFFFE C800 0xFFFE CB00 0xFFFE D800 REGISTER SET MPU Level 2 Interrupt Handler Registers LCD Controller Registers MPU Timer1 Registers MPU Timer2 Registers MPU Timer3 Registers MPU Watchdog Timer Registers MPU Level 1 Interrupt Handler Registers System DMA Controller Registers ACCESS WIDTH 32 32 32 32 32 32 32 16 ACCESS WIDTH 16 16 16 16 8 16 8 8 32 16 32 32 16 8 8 8 ACCESS WIDTH 8 8 8 16 16 Table 3-3. MPU Public Peripheral Registers MPU BASE ADDRESS 0xFFFB 1000 0xFFFB 3000 0xFFFB 3800 0xFFFB 4000 0xFFFB 4800 0xFFFB 5000 0xFFFB 5800 0xFFFB 6000 0xFFFB 6800 0xFFFB 7800 0xFFFB 9000 0xFFFB A000 0xFFFB A800 0xFFFB C000 0xFFFB D000 0xFFFB D800 REGISTER SET McBSP2 Registers MICROWIRE Registers I2C Registers USB Function Registers RTC Registers MPUIO/Keyboard Registers Pulse Width Light (PWL) Registers Pulse Width Tone (PWT) Registers Camera Interface Registers MMC/SD Registers Timer 32k Registers USB Host Registers Frame Adjustment Counter (FAC) Registers HDQ/1-Wire Registers LED Pulse Generator 1 (LPG1) Registers LED Pulse Generator 2 (LPG2) Registers Table 3-4. MPU/DSP Shared Peripheral Registers MPU BASE ADDRESS 0xFFFB 0000 0xFFFB 0800 0xFFFB 9800 0xFFFC E000 0xFFFC F000 REGISTER SET UART1 Registers UART2 Registers UART3 Registers GPIO Interface Registers Mailbox Registers August 2002 - Revised August 2004 SPRS197D 51 Functional Overview Table 3-5. DSP Public Peripheral Registers (Accessible via MPUI Port) MPU BASE ADDRESS 0xE101 1800 0xE101 2000 0xE101 2800 0xE101 7000 REGISTER SET McBSP1 Registers MCSI2 Registers MCSI1 Registers McBSP3 Registers ACCESS WIDTH 16 16 16 16 Table 3-6. MPU Configuration Registers MPU BASE ADDRESS 0xFFFB C800 0xFFFE 0800 0xFFFE 1000 0xFFFE 1800 0xFFFE C100 0xFFFE C200 0xFFFE C900 0xFFFE CA00 0xFFFE CC00 0xFFFE CE00 0xFFFE CF00 0xFFFE D200 0xFFFE D300 0xFFFE D400 REGISTER SET MPU UART TIPB Bus Switch Registers Ultra Low-Power Device (ULPD) Registers OMAP5910 Configuration Registers Device Die Identification Registers Local Bus Control Registers Local Bus MMU Registers MPU Interface (MPUI) Registers TIPB (Private) Bridge 1 Configuration Registers Traffic Controller Registers MPU Clock/Reset/Power Control Registers DPLL1 Configuration Registers DSP MMU Registers TIPB (Public) Bridge 2 Configuration Registers JTAG Identification Registers ACCESS WIDTH 16 16 32 32 32 32 32 32 32 32 32 32 16 32 3.3 DSP Memory Maps The DSP supports a unified program/data memory map (program and data accesses are made to the same physical space), however peripheral registers are located in a separate I/O space which is accessed via the DSP's port instructions. 3.3.1 DSP Global Memory Map The DSP Subsystem contains 160K bytes of on-chip SRAM (64K bytes of DARAM and 96K bytes of SARAM). The MPU also has access to these memories via the MPUI (MPU Interface) port. The DSP also has access to the shared system SRAM (192K bytes) and both EMIF spaces (EMIFF and EMIFS) via the DSP Memory Management Unit (MMU) which is configured by the MPU. Table 3-7 shows the high-level program/data memory map for the DSP subsystem. DSP data accesses utilize 16-bit word addresses while DSP program fetches utilize byte addressing. Table 3-7. DSP Global Memory Map BYTE ADDRESS RANGE 0x00 0000 - 0x00 FFFF 0x01 0000 - 0x02 7FFF 0x02 8000 - 0x04 FFFF 0x05 0000 - 0xFF 7FFF 0xFF 8000 - 0xFF FFFF WORD ADDRESS RANGE 0x00 0000 - 0x00 7FFF 0x00 8000 - 0x01 3FFF 0x01 4000 - 0x02 7FFF 0x02 8000 - 0x7F BFFF 0x7F C000 - 0x7F FFFF INTERNAL MEMORY DARAM 64K bytes SARAM 96K bytes Reserved EXTERNAL MEMORY Managed by DSP MMU PDROM (MPNMC = 0) Managed by DSP MMU (MPNMC =1) This space could be external memory or internal shared system memory depending on the DSP MMU configuration. 52 SPRS197D August 2002 - Revised August 2004 Functional Overview 3.3.2 On-Chip Dual-Access RAM (DARAM) The DARAM is located in the byte address range 000000h-00FFFFh and is composed of eight blocks of 8K bytes each (see Table 3-8). Each DARAM block can perform two accesses per cycle (two reads, two writes, or a read and a write). Table 3-8. DARAM Blocks BYTE ADDRESS RANGE 0x00 0000 - 0x00 1FFF 0x00 2000 - 0x00 3FFF 0x00 4000 - 0x00 5FFF 0x00 6000 - 0x00 7FFF 0x00 8000 - 0x00 9FFF 0x00 A000 - 0x00 BFFF 0x00 C000 - 0x00 DFFF 0x00 E000 - 0x00 FFFF WORD ADDRESS RANGE 0x00 0000 - 0x00 0FFF 0x00 1000 - 0x001FFF 0x00 2000 - 0x00 2FFF 0x00 3000 - 0x00 3FFF 0x00 4000 - 0x00 4FFF 0x00 5000 - 0x00 5FFF 0x00 6000 - 0x00 6FFF 0x00 7000 - 0x00 7FFF MEMORY BLOCK DARAM 0 DARAM 1 DARAM 2 DARAM 3 DARAM 4 DARAM 5 DARAM 6 DARAM 7 3.3.3 On-Chip Single-Access RAM (SARAM) The SARAM is located at the byte address range 010000h-03FFFFh and is composed of 12 blocks of 8K bytes each (see Table 3-9). Each SARAM block can perform one access per cycle (one read or one write). Table 3-9. SARAM Blocks BYTE ADDRESS RANGE 0x01 0000 - 0x01 1FFF 0x01 2000 - 0x01 3FFF 0x01 4000 - 0x01 5FFF 0x01 6000 - 0x01 7FFF 0x01 8000 - 0x01 9FFF 0x01 A000 - 0x01 BFFF 0x01 C000 - 0x01 DFFF 0x01 E000 - 0x01 FFFF 0x02 0000 - 0x02 1FFF 0x02 2000 - 0x02 3FFF 0x02 4000 - 0x02 5FFF 0x02 6000 - 0x02 7FFF WORD ADDRESS RANGE 0x00 8000 - 0x00 8FFF 0x00 9000 - 0x00 9FFF 0x00 A000 - 0x00 AFFF 0x00 B000 - 0x00 BFFF 0x00 C000 - 0x00 CFFF 0x00 D000 - 0x00 DFFF 0x00 E000 - 0x00 EFFF 0x00 F000 - 0x00 FFFF 0x01 0000 - 0x01 0FFF 0x01 1000 - 0x01 1FFF 0x01 2000 - 0x01 2FFF 0x01 3000 - 0x01 3FFF MEMORY BLOCK SARAM 0 SARAM 1 SARAM 2 SARAM 3 SARAM 4 SARAM 5 SARAM 6 SARAM 7 SARAM 8 SARAM 9 SARAM 10 SARAM 11 August 2002 - Revised August 2004 SPRS197D 53 Functional Overview 3.3.4 DSP I/O Space Memory Map The DSP I/O space is a separate address space from the data/program memory space. The I/O space is accessed via the DSP's port instructions. The Public and Shared peripheral registers are also accessible by the MPU through the MPUI (MPU Interface) port. The DSP I/O space is accessed using 16-bit word addresses. The following tables specify the DSP base addresses where each set of registers is accessed. All accesses to these registers must utilize the appropriate access width as indicated in the tables. Accessing registers with the incorrect access width may cause unexpected results including a TI Peripheral Bus (TIPB) bus error and associated TIPB interrupt. Refer to Sections 3.16 and 3.17 for more detail about each of these register sets including individual register addresses, register names, descriptions, supported access types (read, write or read/write) and reset values. Table 3-10. DSP Private Peripheral Registers DSP BASE ADDRESS 0x00 0C00 0x00 2800 0x00 2C00 0x00 3000 0x00 3400 0x00 3800 0x00 4800 REGISTER SET DSP DMA Controller Registers DSP Timer1 Registers DSP Timer2 Registers DSP Timer3 Registers DSP Watchdog Timer Registers DSP Interrupt Interface Registers Level2 Interrupt Handler Registers ACCESS WIDTH 16 16 16 16 16 16 16 Table 3-11. DSP Public Peripheral Registers DSP BASE ADDRESS 0x00 8C00 0x00 9000 0x00 9400 0x00 B800 REGISTER SET McBSP1 Registers MCSI2 Registers MCSI1 Registers McBSP3 Registers ACCESS WIDTH 16 16 16 16 Table 3-12. DSP/MPU Shared Peripheral Registers DSP BASE ADDRESS 0x00 8000 0x00 8400 0x00 CC00 0x00 F000 0x00 F800 REGISTER SET UART1 Registers UART2 Registers UART3 Registers GPIO Interface Registers Mailbox Registers ACCESS WIDTH 8 8 8 16 16 Table 3-13. DSP Configuration Registers DSP BASE ADDRESS 0x00 0000 0x00 0800 0x00 1400 0x00 4000 0x00 E400 REGISTER SET DSP TIPB Bridge Configuration Registers DSP EMIF Configuration Registers DSP I-Cache Registers DSP Clock Mode Registers DSP UART TIPB Bus Switch Registers ACCESS WIDTH 16 16 16 16 16 54 SPRS197D August 2002 - Revised August 2004 Functional Overview 3.4 DSP External Memory (Managed by MMU) When the DSP MMU is off, the 24 address lines are directly copied to the traffic controller without any modification. There is no virtual-to-physical address translation. All the addresses between 0x05 0000 and 0x00FF F800 (0x00FF FFFF if DSP bit MP/MC = 1) are redirected to the first sector of flash (CS0) in the shared memory space (shared by MPU and DSP). Byte Address 0x00 0000 0x05 0000 DSP Memory Internal RAM Shared Memory EMIFS (FLASH CS0) Reserved EMIFS (FLASH CS1) Reserved EMIFS (FLASH CS2) 0xFF 8000 ROM 0xFF FFFF Reserved EMIFS (FLASH CS3) Reserved EMIFF (SDRAM) Reserved IMIF (Internal SRAM) 0x2000 0000 0x2002 FFFF 0x1000 0000 0x13FF FFFF 0x0C00 0000 0x0DFF FFFF 0x0800 0000 0x09FF FFFF 0x0400 0000 0x05FF FFFF Byte Address 0x0000 0000 0x01FF FFFF Figure 3-2. DSP MMU Off August 2002 - Revised August 2004 SPRS197D 55 Functional Overview When the DSP MMU is on, the 24 address lines (virtual address) are relocated within a physical 32-bit address by the DSP MMU. The DSP MMU is controlled by the MPU. Byte Address 0x00 0000 0x05 0000 Shared Memory EMIFS (FLASH CS0) Reserved EMIFS (FLASH CS1) Reserved EMIFS (FLASH CS2) Reserved EMIFS (FLASH CS3) Reserved EMIFF (SDRAM) Reserved IMIF (Internal SRAM) 0x2000 0000 0x2002 FFFF 0x1000 0000 0x13FF FFFF 0x0C00 0000 0x0DFF FFFF 0x0800 0000 0x09FF FFFF 0x0400 0000 0x05FF FFFF Byte Address 0x0000 0000 0x01FF FFFF DSP Memory Internal RAM FLASH CS0 0xFF 8000 ROM 0xFF FFFF Figure 3-3. DSP MMU On 56 SPRS197D August 2002 - Revised August 2004 Functional Overview 3.5 MPU and DSP Private Peripherals The MPU and DSP each have their own separate private peripheral bus. Peripherals on each of these private buses may only be accessed by their respective processors. For instance, the DSP timers on the DSP private peripheral bus are not accessible by the MPU or the System DMA controller. 3.5.1 Timers The MPU and DSP each have their own three 32-bit timers available on their respective private TI Peripheral Bus (TIPB). These timers are used by the operating systems to provide general-purpose housekeeping functions, or in the case of the DSP, to also provide synchronization of real-time processing functions. These timers may be configured either in auto-reload or one-shot mode with on-the-fly read capability. The timers generate an interrupt to the respective processor (MPU or DSP) when the timer's down-counter is equal to zero. 3.5.2 32k Timer (MPU only) The MPU has one 32k Timer that runs on the 32-kHz clock as opposed to the MPU subsystem domain clock. The MPU subsystem operating system (OS) requires interrupts at regular time intervals for OS scheduling purpose (typically 1 ms to 30 ms). These time intervals can be generated using the MPU's three 32-bit general-purpose timers. However, these timers cannot be used in sleep modes when the system clock is not operating. Therefore, a 32-kHz clock-based timer is needed to provide the required OS timing interval. 3.5.3 Watchdog Timer The MPU and DSP each have a single Watchdog Timer. Each watchdog timer can be configured as either a watchdog timer or a general-purpose timer. A watchdog timer requires that the MPU or DSP software or OS periodically write to the appropriate WDT count register before the counter underflows. If the counter underflows, the WDT generates a reset to the appropriate processor (MPU or DSP). The DSP WDT resets only the DSP processor while the MPU WDT resets both processors (MPU and DSP). The watchdog timers are useful for detecting user programs that are stuck in an infinite loop, resulting in loss of program control or in a runaway condition. When used as a general-purpose timer, the WDT is a 16-bit timer configurable either in autoreload or one-shot mode with on-the-fly read capability. The timer generates an interrupt to the respective processor (MPU or DSP) when the timer's down-counter is equal to zero. 3.5.4 Interrupt Handlers The MPU and DSP each have two levels of interrupt handling, allowing up to 39 interrupts to the DSP and 63 interrupts to the MPU. 3.5.5 LCD Controller The OMAP5910 device includes an LCD Controller that interfaces with most industry-standard LCDs. The LCD Controller is configured by the MPU and utilizes a dedicated channel on the System DMA to transfer data from the frame buffer. The frame buffer can be implemented using the internal shared SRAM (192K bytes) or optionally using external SDRAM via the EMIFF. Using the frame buffer as its data source, the System DMA must provide data to the FIFO at the front end of the LCD controller data path at a rate sufficient to support the chosen display mode and resolution. Optimal performance is achieved when using the internal SRAM as the frame buffer. The panel size is programmable, and can be any width (line length) from 16 to 1024 pixels in 16-pixel increments. The number of lines is set by programming the total number of pixels in the LCD. The total frame size is programmable up to 1024 x 1024. However, frame sizes and frame rates supported in specific applications will depend upon the available memory bandwidth allowed by the specific application as well as the maximum configurable pixel clock rate. August 2002 - Revised August 2004 SPRS197D 57 Functional Overview The screen is intended to be mapped to the frame buffer as one contiguous block where each horizontal line of pixels is mapped to a set of consecutive bytes of words in the frame memory. The principle features of the LCD controller are: * * * * * * * * Dedicated 64-entry x 16-bit FIFO Dedicated LCD DMA channel for LCD Programmable display including support for 2-, 4-, 8-, 12-, and 16-bit graphics modes Programmable display resolutions up to 1024 pixels by 1024 lines (assuming sufficient system bandwidth) Support for passive monochrome (STN) displays Support for passive color (STN) displays Support for active color (TFT) displays Patented dithering algorithm, providing: - 15 grayscale levels for monochrome passive displays - 3375 colors for color passive displays - 65536 colors for active color displays - 256-entry x 12-bit palette Programmable pixel rate Pixel clock plus horizontal and vertical synchronization signals ac-bias drive signal Active display enable signal 256-entry x 12-bit palette Dual-frame buffers * * * * * * 3.6 MPU Public Peripherals Peripherals on the MPU Public Peripheral bus may only be accessed by the MPU and the System DMA Controller, which is configured by the MPU. This bus is called a public bus because it is accessible by the System DMA controller. The DSP cannot access peripherals on this bus. 3.6.1 USB Host Controller The OMAP5910 USB host controller communicates with USB devices at the USB low-speed (1.5M-bit/s maximum) and full-speed (12M-bit/s maximum) data rates. The controller is USB compliant. For additional information, see the Universal Serial Bus Specification, Revision 2.0 and the OpenHCI - Open Host Controller Interface Specification for USB, Release 1.0a, hereafter called the OHCI Specification for USB. The OMAP5910 USB host controller implements the register set and makes use of the memory data structures which are defined in the OHCI Specification for USB. These registers and data structures are the mechanism by which a USB host controller driver software package may control the OMAP5910 USB host controller. The USB host controller is connected to the MPU public peripheral bus for MPU access to registers. The USB host controller gains access to the data structures in system memory via the internal Local Bus interface. The OMAP5910 device implements a variety of signal multiplexing options that allows use of the USB host controller with any of the three available USB interfaces on the device. One of these interfaces utilizes an integrated USB transceiver, while the other two require external transceivers. The host controller can support up to three downstream ports. The OMAP5910 USB host controller implementation does not implement every aspect of the functionality defined in the OHCI Specification for USB. The differences focus on power switching, overcurrent reporting, and the OHCI ownership change interrupt. Other restrictions are imposed by OMAP5910 system memory addressing mechanisms and the effects of the OMAP5910 pin-multiplexing options. 58 SPRS197D August 2002 - Revised August 2004 Functional Overview 3.6.2 USB Function Peripheral The USB Function peripheral provides a full-speed Function interface between the MPU and the USB wire. The module handles USB transactions with minimal MPU intervention and is fully compliant to USB standard. The USB Function module supports one control endpoint (EP0), up to 15 IN endpoints, and up to 15 OUT endpoints. The exact endpoint configuration is software-programmable. The specific items of a configuration for each endpoint are: the size in bytes, the direction (IN, OUT), the type (bulk/interrupt or isochronous), and the associated endpoint number. The USB Function module also supports the use of three System DMA channels for IN endpoints and three System DMA channels for OUT endpoints for either bulk/interrupt or isochronous transactions. The OMAP5910 device implements a variety of signal-multiplexing options that allow use of the USB Function peripheral with any one of the three available USB interfaces on the device. One of these interfaces utilizes an integrated USB transceiver, while the other two require external transceivers. The USB Function can only utilize one of these ports at a time. The other ports may be used simultaneously by the USB Host controller peripheral. 3.6.3 Multichannel Buffered Serial Port (McBSP) The Multichannel Buffered Serial Port (McBSP) provides a high-speed, full-duplex serial port that allow direct interface to audio codecs, and various other system devices. The MPU public peripheral bus has access to one McBSP, which is McBSP2. The McBSP provides: * * * * Full-duplex communication Double-buffer data registers, which allow a continuous data stream Independent framing and clocking for receive and transmit Direct interface to: - T1/E1 framers - MVIP switching-compatible and ST-BUS compliant devices - IOM-2 compliant device - AC97-compliant device - I2S-compliant device - Serial peripheral interface (SPI) Multichannel transmit and receive of up to 128 channels A wide selection of data sizes, including: 8, 12, 16, 20, 24, or 32 bits -law and A-law companding Programmable polarity for both frame synchronization and data clocks Programmable internal clock and frame generation NOTE: All of the standard McBSP pins are not necessarily available on every McBSP on the OMAP5910 device. In the case of the MPU's McBSP2, the following pins are available: * * * CLKX and CLKR (transmit and receive clocks) FSX and FSR (transmit and receive frame syncs) DX and RX (transmit and receive data) In addition, the McBSP has the following capabilities: * * * * * The functional clock to the McBSP2 peripheral is configurable to the DPLL clock rate with a divider of 1, 2, 4, or 8. McBSP2 does not have a CLKS external clock reference pin. Therefore, if the McBSP2 Sample Rate Generator (SRG) is used, the only reference clock available to the Sample Rate Generator is a programmable clock from the MPU domain. August 2002 - Revised August 2004 SPRS197D 59 Functional Overview 3.6.4 I 2C Master/Slave Interface The I2C Master/Slave Interface is compliant to Philips I 2C-Bus Specification Version 2.1 master bus. The I2C controller supports the multimaster mode, which allows more than one device capable of controlling the bus to be connected to it. Including the OMAP5910 device, each I2C device is recognized by a unique address and can operate as either transmitter or receiver, depending on the function of the device. In addition to being a transmitter or receiver, a device connected to the I2C bus can also be considered as master or slave when performing data transfers. The I2C Interface supports the following features: * * * * * * * * * * * * Compliant to Philips I 2C-Bus Specification Version 2.1 Support standard mode (up to 100K bits/s) and Fast mode (up to 400K bits/s) 7-bit and 10-bit device addressing modes General call Start/Restart/Stop Multimaster transmitter/slave receiver mode Multimaster receiver/slave transmitter mode Combined master transmit/receive and receive/transmit mode Built-in FIFO for buffered read or write Module enable/disable capability Programmable clock generation Supports use of two DMA channels The I2C Interface does not support the following features: * * High-speed (HS) mode for transfer rates up to 3.4M bits C-bus compatibility mode 3.6.5 MICROWIRE Serial Interface The MICROWIRE interface is a serial synchronous interface that can drive up to four serial external components. The interface is compatible with the MICROWIRE standard and is seen as the master. MICROWIRE is typically used to transmit control and status information to external peripheral devices or to transmit data to or from small nonvolatile memories such as serial EEPROMs or serial Flash devices. 3.6.6 Multimedia Card/Secure Digital (MMC/SD) Interface The MMC/SD Interface controller provides an interface to MMC or SD memory cards. The controller handles MMC/SD transactions with minimal MPU intervention, allowing optional use of two system DMA channels for transfer of data. The following combination of external devices is supported: * * One or more MMC memory cards sharing the same bus. One single SD memory card. NOTE: Other combinations such as two SD cards or one MMC card with one SD card are not supported. The MPU software must manage transaction semantics, while the MMC/SD controller deals with MMC/SD protocol at the transmission level: packing data, adding the CRC, generating the start/end bit and checking for syntactical correctness. SD mode wide bus width is also supported. I2C Bus is a trademark of Philips Electronics N.V. 60 SPRS197D August 2002 - Revised August 2004 Functional Overview 3.6.7 HDQ/1-Wire Interface This module allows implementation of both HDQ and the 1-Wire protocols. These protocols use a single wire to communicate between a master and a slave. The HDQ/1-Wire pin is open-drain and requires an external pullup resistor. HDQ and 1-Wire interfaces can be found on commercially available battery management and power management devices. The interface can be used to send command and status information between OMAP5910 and such a battery or power management device. 3.6.8 Camera Interface The camera interface is an 8-bit external port which may be used to accept data from an external camera sensor. The interface handles multiple image formats synchronized on vertical and horizontal synchronization signals. Data transfer to the camera interface may be done synchronously or asynchronously. The camera interface module converts the 8-bit data transfers into 32-bit words and utilizes a 128-word buffer to facilitate efficient data transfer to memory. Data may be transferred from the camera interface buffer to internal memory by the system DMA controller or directly by the MPU. The interface may utilize an externally driven clock at rates up to 13 MHz or may optionally provide an output reference clock at rates of 8 MHz, 9.6 MHz, or 24 MHz when the camera interface is configured for clocking from the internal 48 MHz. When the camera interface is configured to obtain clocking from the base oscillator frequency (12 MHz or 13 MHz), the camera interface clock is configurable to operate at the base frequency or one half the base frequency (6 MHz or 6.5 MHz). 3.6.9 MPUIO/Keyboard Interface The MPUIO pins may be used as either general-purpose I/O for the MPU or as a Keyboard Interface to a 6 x 5 or 8 x 8 keypad array. If a 6 x 5 keypad array is implemented, the unused MPUIO pins may be used as GPIO. When used as GPIO, each pin may be configured individually as either an output or an input, and they may be individually configured to generate MPU interrupts based on a level change (falling or rising) after a debouncing process. These MPUIO interrupts may be used to wake up the device from deep-sleep mode using the 32-kHz clock. The MPUIO pins may also be used as a keyboard interface. The keyboard interface provides the following pins: * * KB.R[7:0] input pins for row lines KB.C[7:0] output pins for column lines To allow key-press detection, all input pins (KB.Rx) are pulled up to DVDD and all output pins (KB.Cx) are driven low level. The KB.R[7:0] and KB.C[7:0] pins should be connected to an external keyboard matrix such that when a key on the matrix is pressed, the corresponding row and column lines are shorted together. Any action on a key generates an interrupt to the MPU, which then scans the column lines in a particular sequence to determine which key or keys have been pressed. 3.6.10 Pulse-Width Light (PWL) The Pulse-Width Light (PWL) module provides control of the LCD or keypad backlighting by employing a random sequence generator. This voltage-level control technique decreases the spectral power at the modulator harmonic frequencies. The module uses a switchable 32-kHz clock. 3.6.11 Pulse-Width Tone (PWT) The Pulse-Width Tone (PWT) module generates a modulated frequency signal for use with an external buzzer. The frequency is programmable between 349 Hz and 5276 Hz with 12 half-tone frequencies per octave. The volume level of the output is also programmable. August 2002 - Revised August 2004 SPRS197D 61 Functional Overview 3.6.12 LED Pulse Generator There are two separate LED Pulse Generator (LPG) modules. Each LPG module provides an output for an indication LED. The blinking period is programmable between 152 ms and 4 s or the LED can be switched on or off permanently. 3.6.13 Real-Time Clock The Real-Time Clock (RTC) module provides an embedded RTC for use in applications which need to track real time. This peripheral is not an ultra-low-power module--meaning that the RTC module cannot be powered independently without powering the OMAP5910 MPU core. Therefore, if an ultra-low-power RTC is desired for a system application, an external RTC should be used. The RTC module has the following features: * * * * * Time information (seconds/minutes/hours) directly in BCD code Calendar information (day/month/year/day of the week) directly in BCD code up to year 2099 Interrupts generation, periodically (1s/1m/1h/1d period) or at a precise time of the day (alarm function) 30-s time correction Oscillator frequency calibration 3.6.14 Frame Adjustment Counter The frame adjustment counter (FAC) is a simple peripheral that counts the number of rising edges of one signal (start of frame interrupt of the USB Function) during a programmable number of rising edges of a second signal (transmit frame synchronization of McBSP2). The FAC may only be used with these specific USB Function and McBSP2 signals. The count value can be used by system-level software to adjust the duration of the two time domains with respect to each other to reduce overflow and underflow. If the data being transferred is audio data, this module can be part of a solution that reduces pops and clicks. The FAC module generates one second-level interrupt to the MPU. 3.7 DSP Public Peripherals Peripherals on the DSP Public Peripheral bus are directly accessible by the DSP and DSP DMA. These peripherals may also be accessed by the MPU and System DMA Controller via the MPUI interface. The MPUI interface must be properly configured to allow this access. 3.7.1 Multichannel Buffered Serial Port (McBSP) The Multichannel Buffered Serial Port (McBSP) provides a high-speed, full-duplex serial port that allow direct interface to audio codecs and various other system devices. Refer to Section 3.6.3 for a list of features provided by the McBSP. The DSP public peripheral bus has access to two McBSPs: McBSP1 and McBSP3. NOTE: All of the standard McBSP pins are not necessarily available on every McBSP on the OMAP5910 device. In the case of the two DSP McBSPs, the following pins are available: * McBSP1 pins: - - - - * - - - CLKX (transmit clock) FSX (transmit frame sync) DX and DR (transmit and receive data) CLKS (external reference to Sample Rate Generator) CLKX (transmit clock) FSX (transmit frame sync) DX and DR (transmit and receive data) McBSP3 pins: 62 SPRS197D August 2002 - Revised August 2004 Functional Overview Because McBSP1 and McBSP3 do not have the CLKR and FSR pins available, the transmit clock and frame sync pins (CLKX and FSX) must be used for bit clock and frame synchronization on both the transmit and receive channels of these McBSPs. The functional clock to McBSP1 and McBSP3 is fixed at the OMAP5910 base operating frequency (12 MHz or 13 MHz). The bit-clock rate for these McBSPs is therefore limited to 6 or 6.5 MHz (one half the base frequency). Only McBSP1 has the CLKS pin available. If the sample rate generator (SRG) is used on McBSP1, the reference clock to the SRG can be configured to be either an external reference provided on the CLKS pin, or the internal base (12- or 13-MHz) device clock. However, if the SRG is used on McBSP3, the only reference clock available to this SRG is the base device clock as clock reference. 3.7.2 Multichannel Serial Interface (MCSI) The multichannel serial interface (MCSI) provides flexible serial interface with multichannel transmission capability. The MCSI allows the DSP to access a variety of external devices, such as audio codecs and other types of analog converters. The DSP public peripheral bus has access to two MCSIs: MCSI1 and MCSI2. These MCSIs provide full-duplex transmission and master or slave clock control. All transmission parameters are configurable to cover the maximum number of operating conditions. The MCSIs have the following features: * * * * * * * * * * * * * * * * Master or slave clock control (transmission clock and frame synchronization pulse) Programmable transmission clock frequency (master mode) up to one half the OMAP5910 base frequency (12 or 13 MHz) Reception clock frequency (slave mode) of up to the base frequency (12 or 13 MHz) Single-channel or multichannel (x16) frame structure Programmable word length: 3 to 16 bits Full-duplex transmission Programmable frame configuration Continuous or burst transmission Normal or alternate framing Normal or inverted frame and clock polarities Short or long frame pulse Programmable oversize frame length Programmable frame length Programmable interrupt occurrence time (TX and RX) Error detection with interrupt generation on wrong frame length System DMA support for both TX and RX data transfers 3.8 Shared Peripherals The shared peripherals are connected to both the MPU Public Peripheral bus and the DSP Public Peripheral bus. In the case of the UARTs, these connections are achieved via a TI Peripheral Bus Switch, which must be configured to allow MPU or DSP access to the UARTs. The other shared peripherals have permanent connections to both public peripheral buses, although read and write accesses to each peripheral register may differ. 3.8.1 Universal Asynchronous Receiver/Transmitter (UART) The OMAP5910 device has three Universal Asynchronous Receiver/Transmitter (UART) peripherals which are accessible on the DSP public and MPU public peripheral buses. A TI peripheral bus switch configured by the MPU allows either TIPB access to these UART peripherals. All three UARTs are standard 16C750-compatible UARTs implementing an asynchronous transfer protocol with various flow control options. Two of the three UARTs (UART1 and UART2) have autobaud capability to automatically determine and adjust to the baud rate of the external connected device. One of the UARTs (UART3) can function as a general UART or can optionally function as an IrDA interface. August 2002 - Revised August 2004 SPRS197D 63 Functional Overview The main features of the UART peripherals include: * * * * * * * * * * * * Selectable UART/autobaud modes (autobauding on UART1 and UART2) with autobauding between 1200 bits/s and 115.2K bits/s Dual 64-entry FIFOs for received and transmitted data payload Programmable and selectable transmit and receive FIFO trigger levels for DMA and interrupt generation Programmable sleep mode Complete status-reporting capabilities in both normal and sleep mode Frequency prescaler values from 0 to 65535 to generate the appropriate baud rates Interrupt request generated if multiple System DMA requests Baud rate from 300 bits/s up to 1.5M bits/s Software/hardware flow control Programmable XON/XOFF characters Programmable auto-RTS and auto-CTS Programmable serial interface characteristics - 5-, 6-, 7-, or 8-bit characters - Even-, odd-, or no-parity bit generation and detection - 1, 1.5, or 2 stop-bit generation - False start bit detection - Line break generation and detection - Fully prioritized interrupt system controls - Internal test and loopback capabilities - Modem control functions (CTS, RTS, DSR, DTR) NOTE: DSR and DTR are only available on UART1 and UART3. The IrDA functions available on UART3 are as follows: * * * Slow infrared (SIR) operations Framing error, cyclic redundancy check (CRC) error, abort pattern (SIR) detection 8-entry status FIFO (with selectable trigger levels) available to monitor frame length and frame errors 3.8.2 General-Purpose I/O (GPIO) There are up to 14 shared GPIO pins on the OMAP5910 device which may be accessed and controlled by either the DSP public peripheral bus or the MPU public peripheral bus. Each GPIO pin is independently configurable to be used by either the DSP or MPU. The MPU controls which processor owns each GPIO pin by configuring a pin control register that only the MPU can access. Each GPIO pin can be used as either an input or output pin with GPIO inputs being synchronized internally to a peripheral clock. GPIO inputs may also optionally be configured to generate an interrupt condition to the processor which owns the GPIO pin. The sense of the interrupt condition is configurable such that either a high-to-low or low-to-high transition causes the interrupt condition. Some of the GPIO pins are multiplexed with other interface pins specific to other device peripherals. Refer to Table 2-3 to decide which GPIO pins are multiplexed with other peripheral signals. 3.8.3 Mailbox Registers Four sets of shared mailbox registers are available for communication between the DSP and MPU. These registers are discussed further in Section 3.12, Interprocessor Communication. 64 SPRS197D August 2002 - Revised August 2004 Functional Overview 3.9 System DMA Controller The System Direct Memory Access (DMA) controller transfers data between points in the memory space without intervention by the MPU. The System DMA allows movements of data to and from internal memory, external memory, and peripherals to occur in the background of MPU operation. It is designed to off-load the block data transfer function from the MPU processor. The System DMA is configured by the MPU via the MPU private peripheral bus. The System DMA controller has nine independent general-purpose channels and seven ports that it may transfer to/from. An additional tenth channel is dedicated for use with the LCD controller. Of the seven available ports, the DMA transfers may occur between any two ports with the exception of the LCD port, which may only be used as a destination with the EMIFF or IMIF as the source. For maximum transfer efficiency, all nine channels are independent. This means that if multiple channels are exclusively accessing different ports, then simultaneous transfers performed by the channels will occur uninhibited. If the multiple channels are accessing common ports, however, some arbitration cycles will be necessary. Arbitration occurs in a round-robin fashion with configurable priority for each channel (high or low). The basic functional features of the system DMA controller are as follows: * * * * * * * * * * * Nine general-purpose and one dedicated (LCD) DMA channels Round-robin arbitration scheme with programmable priorities Concurrent DMA transfer capability Start of transfer on peripheral request or host request Byte-alignment and Byte-packing/unpacking capability Burst transfer capability (IMIF, EMIFF, EMIFS, LCD, and Local ports) Time-out counter for each DMA channel to prevent a channel locking on a memory location or peripheral. Constant, post-incrementing, and Single- or Double-Indexed addressing modes Autoinitialization for multiple block transfers without MPU intervention Access available to all of the memory range (physical memory mapping and TIPB space) Seven ports are available for different kinds of hardware resources. - - - - - - - * EMIFS port (allowing access to external asynchronous memory or devices) EMIFF port (allowing access to external SDRAM) IMIF port (allowing access to 192K bytes of shared SRAM) MPUI port (allowing access to DSP memory and peripherals) TIPB port (allowing peripheral register access) Local port (used for Host USB only) LCD port (allowing transfers to the LCD controller) Memory-to-memory transfer granularity of 8, 16, and 32 bits. August 2002 - Revised August 2004 SPRS197D 65 Functional Overview 3.10 DSP DMA Controller The DSP subsystem has its own dedicated DMA Controller, which is entirely independent of the MPU or the System DMA Controller. The DSP DMA Controller has many of the same major features that the System DMA Controller possesses (see Section 3.9). The DSP DMA Controller has six generic channels and five physical ports available for source or destination data. These five ports are the SARAM port, DARAM port, EMIF (External memory port), DSP TIPB port, and MPUI port. The DSP may configure the DSP DMA Controller to transfer data between the SARAM, DARAM, EMIF, and TIPB ports, but the MPUI port is a dedicated port used for MPU or System DMA initiated transfers to DSP subsystem resources. The SARAM and DARAM ports are used to access local DSP memories and the TIPB port is used to access the registers of the DSP peripherals. The EMIF port of the DSP DMA controller is used to access the Traffic Controller via the DSP MMU (Memory Management Unit). 3.11 Traffic Controller (Memory Interfaces) The Traffic Controller (TC) manages all accesses by the MPU, DSP, System DMA, and Local Bus to the OMAP5910 system memory resources. The TC provides access to three different memory interfaces: External Memory Interface Slow (EMIFS), External Memory Interface Fast (EMIFF), and Internal Memory Interface (IMIF). The IMIF allows access to the 192K bytes of on-chip SRAM. The EMIFS interface provides 16-bit-wide access to asynchronous or synchronous memories or devices such as Intel StraFlashTM memory (28FxxxJ3A, Static Byte Enable) and Asynchronous SRAMs. The EMIFF Interface provides access to 16-bit-wide access to standard SDRAM memories and the IMIF provides access to the 192K bytes of on-chip SRAM. The TC provides the functions of arbitrating contending accesses to the same memory interface from different initiators (MPU, DSP, System DMA, Local Bus), synchronization of accesses due to the initiators and the memory interfaces running at different clock rates, and the buffering of data allowing burst access for more efficient multiplexing of transfers from multiple initiators to the memory interfaces. The TC's architecture allows simultaneous transfers between initiators and different memory interfaces without penalty. For instance, if the MPU is accessing the EMIFF at the same time, the DSP is accessing the IMIF, transfers may occur simultaneously since there is no contention for resources. There are three separate ports to the TC from the System DMA (one for each of the memory interfaces), allowing for greater bandwidth capability between the System DMA and the TC. 66 SPRS197D August 2002 - Revised August 2004 Functional Overview 3.12 Interprocessor Communication Several mechanisms allow for communication between the MPU and the DSP on the OMAP5910 device. These include mailbox registers, MPU Interface, and shared memory space. 3.12.1 MPU/DSP Mailbox Registers The MPU and DSP processors may communicate with each other via a mailbox-interrupt mechanism. This mechanism provides a very flexible software protocol between the processors. There are four sets of mailbox registers located in public TIPB space. The registers are shared between the two processors, so the MPU and DSP may both access these registers within their own public TIPB space, but read/write accessibility of each register is different for each processor. There are four sets of mailbox registers: two for the MPU to send messages and issue an interrupt to the DSP, the other two for the DSP to send messages and issue an interrupt to the MPU. Each set of mailbox registers consists of two 16-bit registers and a 1-bit flag register. The interrupting processor can use one 16-bit register to pass a data word to the interrupted processor and the other 16-bit register to pass a command word. Communication is achieved when one processor writes to the appropriate command word register which causes an interrupt to the other processor and sets the appropriate flag register. The interrupted processor acknowledges by reading the command word which causes the flag register to be cleared. An additional data-word register is also available in each mailbox register set to optionally communicate two words of data between the processors for each interrupt instead of just communicating the command word. The information communicated by the command and data words are entirely user-defined. The data word may be optionally used to indicate an address pointer or status word. 3.12.2 MPU Interface (MPUI) The MPU interface (MPUI) allows the MPU and the system DMA controller to communicate with the DSP and its peripherals. The MPUI allows access to the full memory space (16M bytes) of the DSP and the DSP public peripheral bus. Thus, the MPU and System DMA Controller both have read and write access to the complete DSP I/O space (128K bytes), including the control registers of the DSP public peripherals. The MPUI port supports the following features: * Four access modes: - - - - * * * * * * * Shared-access mode (SAM) for MPU access of DSP SARAM, DARAM, and external memory interface Shared-access mode (SAM) for peripheral bus access Host-only mode (HOM) for SARAM access Host-only mode (HOM) for peripheral bus access Interrupt to MPU if access time-out occurs Programmable priority scheme (MPU vs. DMA) Packing and unpacking of data (16 bits to 32 bits, and vice versa) 32-bit single access support Software control endianism conversion System DMA capability to full DSP memory space (16M bytes) System DMA capability to the DSP public TIPB peripherals (up to 128K bytes space) This port can be used for many functions, such as: MPU loading of program code into DSP program memory space, sharing of data between MPU and DSP, implementing interprocessing communication protocols via shared memory, or allowing MPU to use and control DSP Public TIPB Peripherals. August 2002 - Revised August 2004 SPRS197D 67 Functional Overview 3.12.3 MPU/DSP Shared Memory The OMAP5910 device implements a shared memory architecture via the Traffic Controller. Therefore, the MPU and DSP both have access to the same shared SRAM memory (192K bytes) as well as to the EMIFF and EMIFS memory space. Through the DSP Memory Management Unit (MMU), the MPU controls which regions of shared memory space the DSP is allowed to access. By setting up regions of shared memory, and defining a protocol for the MPU and DSP to access this shared memory, an interprocessor communication mechanism may be implemented. This method may be used in conjunction with the mailbox registers to create handshaking interrupts which will properly synchronize the MPU and DSP accesses to shared memory. Utilizing the shared memory in this fashion may be useful when the desired data to be passed between the MPU and DSP is larger than the two 16-bit words provided by each set of mailbox command and data registers. For example, the MPU may need to provide the DSP with a list of pointers to perform a specific task as opposed to a single command and single pointer. Using shared memory and the mailboxes, the DSP could read the list of pointers from shared memory after receiving the interrupt caused by an MPU write to the mailbox command register. 3.13 DSP Hardware Accelerators The TMS320C55x DSP core within the OMAP5910 device utilizes three powerful hardware accelerator modules which assist the DSP core in implementing specific algorithms that are commonly used in video compression applications such as MPEG4 encoders/decoders. These accelerators allow implementation of such algorithms using fewer DSP instruction cycles and dissipating less power than implementations using only the DSP core. The hardware accelerators are utilized via functions from the TMS320C55x Image/Video Processing Library available from Texas Instruments. Utilizing the hardware accelerators, the Texas Instruments Image/Video Processing Library implements many useful functions, which include the following: * * * * Forward and Inverse Discrete Cosine Transform (DCT) (used for video compression/decompression) Motion Estimation (used for compression standards such as MPEG video encoding and H.26x encoding) Pixel Interpolation (enabling high-performance fractal-pixel motion estimation) Flexible 1D/2D Wavelet Processing (useful for JPEG2000, MPEG4, and other compression standards) 3.13.1 DCT/iDCT Accelerator The DCT/iDCT hardware accelerator is used to implement Forward and Inverse DCT (Discrete Cosine Transform) algorithms. These DCT/iDCT algorithms can be used to implement a wide range of video compression standards including JPEG Encode/Decode, MPEG Video Encode/Decode, and H.26x Encode/Decode. 3.13.2 Motion Estimation Accelerator The Motion Estimation hardware accelerator implements a high-performance motion estimation algorithm, enabling MPEG Video encoder or H.26x encoder applications. Motion estimation is typically one of the most computation-intensive operations in video-encoding systems. 3.13.3 Pixel Interpolation Accelerator The Pixel Interpolation Accelerator enables high-performance pixel-interpolation algorithms, which allows for powerful fractal pixel motion estimation when used in conjunction with the Motion Estimation accelerator. Such algorithms provide significant improvement to video-encoding applications. 3.14 Power Supply Connection Examples 3.14.1 Core and I/O Voltage Supply Connections The OMAP5910 device is extremely flexible regarding the implementation of the core and I/O voltage supplies of the device. 68 SPRS197D August 2002 - Revised August 2004 Functional Overview In a typical system, all of the core voltage supplies (CVDDx) may be connected together and powered from one common supply. Likewise, all of the I/O voltage supplies (DVDDx) may be connected together and powered from a common supply. Figure 3-4 illustrates this common system configuration. OMAP5910 Vout = 1.6 V 1.6-V Voltage Supply CVDD CVDD1 CVDD2 CVDD3 CVDD4 CVDDA Vout = 3.3 V 3.3-V Voltage Supply DVDD1 DVDD2 DVDD3 DVDD4 DVDD5 VSS Figure 3-4. Supply Connections for a Typical System Several of the I/O voltage supplies (DVDD3, DVDD4 and DVDD5) are capable of operating at lower voltages (1.8 V nominal) while the other I/O supplies run at 3.3 V nominal. This is advantageous for systems which mix standard 3.3-V devices with low voltage memory devices or other low voltage logic. Refer to Table 2-4 to determine which I/O pins are powered by each of the DVDDx supplies. Figure 3-5 illustrates an example of this type of mixed voltage system configuration. August 2002 - Revised August 2004 SPRS197D 69 Functional Overview OMAP5910 Vout = 1.6 V 1.6-V Voltage Supply CVDD CVDD1 CVDD2 CVDD3 CVDD4 CVDDA Vout = 3.3 V 3.3-V Voltage Supply DVDD1 DVDD2 DVDD3 DVDD4 DVDD5 VSS Vout = 1.8 V 1.8-V Voltage Supply Figure 3-5. Supply Connections for a System With 1.8-V SDRAM In the previous two examples, all CVDDx pins are connected in common. However, the OMAP5910 device has dedicated CVDD pins which supply power to different sections of the chip (as described in Table 2-4, Signal Descriptions). This feature could be useful in prototyping phases to troubleshoot power management features and perform advanced power. By isolating each CVDDx bus from the power source through isolation jumpers or current sense resistors, the current draw into different domains may be measured separately. This type of supply isolation should only be done during prototyping as production system designs should connect all the CVDDx pins together, preferably to a common board plane. NOTE: There is no specific power sequencing for the different voltage supplies as long as all CVDDx and DVDDx voltages are ramped to valid operating levels within 500 ms of one another. Additionally, if certain I/O pins are unused in a specific system application, the DVDDx supply pins which power these I/O must still be connected to valid operating voltage levels. See Section 5.2, Recommended Operating Conditions, for complete voltage requirements on all CVDDx and DVDDx power supply pins. 3.14.2 Core Voltage Noise Isolation Two of the CVDD pins on the OMAP5910 device, CVDDA and CVDD4, are dedicated to supply power for the ULPD DPLL and OMAP DPLL, respectively. In addition to using sound board design principles, these dedicated pins allow for added supply noise isolation circuitry to enable maximum performance from the OMAP5910 DPLLs. An example circuit is shown in Figure 3-6. 70 SPRS197D August 2002 - Revised August 2004 Functional Overview OMAP5910 Dedicated CVDD for ULPD DPLL ULPD DPLL (for USB) OMAP DPLL Dedicated CVDD for USB DPLL VSSw CVDDA CVDD4 CVDDx VDD Common CVDD for Rest of Chip Voltage RegulatorW C = 10 F R = 10 This circuit is provided only as an example. Specific board layout implementation must minimize noise on the OMAP5910 voltage supply pins. Except where stated otherwise in this document, all VSS pins on the OMAP5910 are common and must be connected directly to a common ground; however, the discrete capacitor in the RC filter circuit should be placed as close as possible to the VSS (GZG balls AA1/Y3 or GDY balls E13/K9). For special consideration with respect to the connection of V SS (GZG ball V12 or GDY ball F6), refer to Section 5.6.1, 32-kHz Oscillator and Input Clock. The voltage regulator must be selected to provide a voltage source with minimal low frequency noise. Figure 3-6. External RC Circuit for DPLL CVDD Noise Isolation 3.15 MPU Register Descriptions The following tables describe the MPU registers including register addresses, descriptions, required access widths, access types (R = read, W = write, RW = read/write) and reset values. These tables are organized by function with like peripherals or functions together and are therefore not necessarily in the order of ascending register addresses. NOTE: All accesses to these registers must be of the data access widths indicated to avoid a TIPB bus error condition and a corresponding interrupt. Reserved addresses should never be accessed. August 2002 - Revised August 2004 SPRS197D 71 Functional Overview 3.15.1 * MPU Private Peripheral Registers Timers - MPU Timer 1 Register - MPU Timer 2 Registers - MPU Timer 3 Registers - MPU Watchdog Timer Registers Interrupt Handlers - MPU Level 1 Interrupt Handler Registers - MPU Level 2 Interrupt Handler Registers System Peripherals - System DMA Controller Registers - LCD Controller Registers Table 3-14. MPU Timer 1 Registers The MPU private peripheral registers include the following: * * BYTE ADDRESS FFFE:C500 FFFE:C504 FFFE:C508 REGISTER NAME MPU_CNTL_TIMER_1 MPU_LOAD_TIM_1 MPU_READ_TIM_1 DESCRIPTION MPU Timer 1 Control Timer Register MPU Timer 1 Load Timer Register MPU Timer 1 Read Timer Register ACCESS WIDTH 32 32 32 ACCESS TYPE RW W R RESET VALUE 0000 0000h undef undef Table 3-15. MPU Timer 2 Registers BYTE ADDRESS FFFE:C600 FFFE:C604 FFFE:C608 REGISTER NAME MPU_CNTL_TIMER_2 MPU_LOAD_TIM_2 MPU_READ_TIM_2 DESCRIPTION MPU Timer 2 Control Timer Register MPU Timer 2 Load Timer Register MPU Timer 2 Read Timer Register ACCESS WIDTH 32 32 32 ACCESS TYPE RW W R RESET VALUE 0000 0000h undef undef Table 3-16. MPU Timer 3 Registers BYTE ADDRESS FFFE:C700 FFFE:C704 FFFE:C708 REGISTER NAME MPU_CNTL_TIMER_3 MPU_LOAD_TIM_3 MPU_READ_TIM_3 DESCRIPTION MPU Timer 3 Control Timer Register MPU Timer 3 Load Timer Register MPU Timer 3 Read Timer Register ACCESS WIDTH 32 32 32 ACCESS TYPE RW W R RESET VALUE 0000 0000h undef undef Table 3-17. MPU Watchdog Timer Registers BYTE ADDRESS FFFE:C800 FFFE:C804 FFFE:C804 FFFE:C808 REGISTER NAME MPU_CNTL_TIMER_WD MPU_LOAD_TIM_WD MPU_READ_TIM_WD MPU_TIMER_MODE_WD DESCRIPTION MPU WDT Control Timer Register MPU WDT Load Timer Register MPU WDT Read Timer Register MPU WDT Timer Mode Register ACCESS WIDTH 16 16 16 16 ACCESS TYPE RW W R RW RESET VALUE 0002h FFFFh FFFFh 8000h 72 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-18. MPU Level 1 Interrupt Handler Registers BYTE ADDRESS FFFE:CB00 FFFE:CB04 FFFE:CB08 - FFFE:CB0C FFFE:CB10 FFFE:CB14 FFFE:CB18 FFFE:CB1C FFFE:CB20 FFFE:CB24 FFFE:CB28 FFFE:CB2C FFFE:CB30 FFFE:CB34 FFFE:CB38 FFFE:CB3C FFFE:CB40 FFFE:CB44 FFFE:CB48 FFFE:CB4C FFFE:CB50 FFFE:CB54 FFFE:CB58 FFFE:CB5C FFFE:CB60 FFFE:CB64 FFFE:CB68 FFFE:CB6C FFFE:CB70 FFFE:CB74 FFFE:CB78 FFFE:CB7C FFFE:CB80 FFFE:CB84 FFFE:CB88 FFFE:CB8C FFFE:CB90 FFFE:CB94 FFFE:CB98 FFFE:CB9C MPU_L1_SIR_IRQ_CODE MPU_L1_SIR_FIQ_CODE MPU_L1_CONTROL_REG MPU_L1_ILR0 MPU_L1_ILR1 MPU_L1_ILR2 MPU_L1_ILR3 MPU_L1_ILR4 MPU_L1_ILR5 MPU_L1_ILR6 MPU_L1_ILR7 MPU_L1_ILR8 MPU_L1_ILR9 MPU_L1_ILR10 MPU_L1_ILR11 MPU_L1_ILR12 MPU_L1_ILR13 MPU_L1_ILR14 MPU_L1_ILR15 MPU_L1_ILR16 MPU_L1_ILR17 MPU_L1_ILR18 MPU_L1_ILR19 MPU_L1_ILR20 MPU_L1_ILR21 MPU_L1_ILR22 MPU_L1_ILR23 MPU_L1_ILR24 MPU_L1_ILR25 MPU_L1_ILR26 MPU_L1_ILR27 MPU_L1_ILR28 MPU_L1_ILR29 MPU_L1_ILR30 MPU_L1_ILR31 MPU_L1_ISR REGISTER NAME MPU_L1_ITR MPU_L1_MIR DESCRIPTION Interrupt Register Mask Interrupt Register Reserved IRQ Interrupt Encoded Source Register FIQ Interrupt Encoded Source Register Interrupt Control Register Interrupt 0 Priority Level Register Interrupt 1 Priority Level Register Interrupt 2 Priority Level Register Interrupt 3 Priority Level Register Interrupt 4 Priority Level Register Interrupt 5 Priority Level Register Interrupt 6 Priority Level Register Interrupt 7 Priority Level Register Interrupt 8 Priority Level Register Interrupt 9 Priority Level Register Interrupt 10 Priority Level Register Interrupt 11 Priority Level Register Interrupt 12 Priority Level Register Interrupt 13 Priority Level Register Interrupt 14 Priority Level Register Interrupt 15 Priority Level Register Interrupt 16 Priority Level Register Interrupt 17 Priority Level Register Interrupt 18 Priority Level Register Interrupt 19 Priority Level Register Interrupt 20 Priority Level Register Interrupt 21 Priority Level Register Interrupt 22 Priority Level Register Interrupt 23 Priority Level Register Interrupt 24 Priority Level Register Interrupt 25 Priority Level Register Interrupt 26 Priority Level Register Interrupt 27 Priority Level Register Interrupt 28 Priority Level Register Interrupt 29 Priority Level Register Interrupt 30 Priority Level Register Interrupt 31 Priority Level Register Software Interrupt Set Register 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h ACCESS WIDTH 32 32 ACCESS TYPE RW RW RESET VALUE 0000 0000h FFFF FFFFh August 2002 - Revised August 2004 SPRS197D 73 Functional Overview Table 3-19. MPU Level 2 Interrupt Handler Registers BYTE ADDRESS FFFE:0000 FFFE:0004 FFFE:0008 - FFFE:000C FFFE:0010 FFFE:0014 FFFE:0018 FFFE:001C FFFE:0020 FFFE:0024 FFFE:0028 FFFE:002C FFFE:0030 FFFE:0034 FFFE:0038 FFFE:003C FFFE:0040 FFFE:0044 FFFE:0048 FFFE:004C FFFE:0050 FFFE:0054 FFFE:0058 FFFE:005C FFFE:0060 FFFE:0064 FFFE:0068 FFFE:006C FFFE:0070 FFFE:0074 FFFE:0078 FFFE:007C FFFE:0080 FFFE:0084 FFFE:0088 FFFE:008C FFFE:0090 FFFE:0094 FFFE:0098 FFFE:009C MPU_L2_SIR_IRQ_CODE MPU_L2_SIR_FIQ_CODE MPU_L2_CONTROL_REG MPU_L2_ILR0 MPU_L2_ILR1 MPU_L2_ILR2 MPU_L2_ILR3 MPU_L2_ILR4 MPU_L2_ILR5 MPU_L2_ILR6 MPU_L2_ILR7 MPU_L2_ILR8 MPU_L2_ILR9 MPU_L2_ILR10 MPU_L2_ILR11 MPU_L2_ILR12 MPU_L2_ILR13 MPU_L2_ILR14 MPU_L2_ILR15 MPU_L2_ILR16 MPU_L2_ILR17 MPU_L2_ILR18 MPU_L2_ILR19 MPU_L2_ILR20 MPU_L2_ILR21 MPU_L2_ILR22 MPU_L2_ILR23 MPU_L2_ILR24 MPU_L2_ILR25 MPU_L2_ILR26 MPU_L2_ILR27 MPU_L2_ILR28 MPU_L2_ILR29 MPU_L2_ILR30 MPU_L2_ILR31 MPU_L2_ISR REGISTER NAME MPU_L2_ITR MPU_L2_MIR DESCRIPTION Interrupt Register Mask Interrupt Register Reserved IRQ Interrupt Encoded Source Register FIQ Interrupt Encoded Source Register Interrupt Control Register Interrupt 0 Priority Level Register Interrupt 1 Priority Level Register Interrupt 2 Priority Level Register Interrupt 3 Priority Level Register Interrupt 4 Priority Level Register Interrupt 5 Priority Level Register Interrupt 6 Priority Level Register Interrupt 7 Priority Level Register Interrupt 8 Priority Level Register Interrupt 9 Priority Level Register Interrupt 10 Priority Level Register Interrupt 11 Priority Level Register Interrupt 12 Priority Level Register Interrupt 13 Priority Level Register Interrupt 14 Priority Level Register Interrupt 15 Priority Level Register Interrupt 16 Priority Level Register Interrupt 17 Priority Level Register Interrupt 18 Priority Level Register Interrupt 19 Priority Level Register Interrupt 20 Priority Level Register Interrupt 21 Priority Level Register Interrupt 22 Priority Level Register Interrupt 23 Priority Level Register Interrupt 24 Priority Level Register Interrupt 25 Priority Level Register Interrupt 26 Priority Level Register Interrupt 27 Priority Level Register Interrupt 28 Priority Level Register Interrupt 29 Priority Level Register Interrupt 30 Priority Level Register Interrupt 31 Priority Level Register Software Interrupt Set Register 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h ACCESS WIDTH 32 32 ACCESS TYPE RW RW RESET VALUE 0000 0000h FFFF FFFFh 74 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-20. System DMA Controller Registers BYTE ADDRESS FFFE:D800 FFFE:D802 FFFE:D804 FFFE:D806 FFFE:D808 FFFE:D80A FFFE:D80C FFFE:D80E FFFE:D810 FFFE:D812 FFFE:D814 FFFE:D816 FFFE:D818 FFFE:D81A - FFFE:083E FFFE:D840 FFFE:D842 FFFE:D844 FFFE:D846 FFFE:D848 FFFE:D84A FFFE:D84C FFFE:D84E FFFE:D850 FFFE:D852 FFFE:D854 FFFE:D856 FFFE:D858 FFFE:D85A - FFFE:D87E FFFE:D880 FFFE:D882 FFFE:D884 FFFE:D886 FFFE:D888 FFFE:D88A FFFE:D88C FFFE:D88E FFFE:D890 FFFE:D892 FFFE:D894 FFFE:D896 FFFE:D898 SYS_DMA_CSDP_CH2 SYS_DMA_CCR_CH2 SYS_DMA_CICR_CH2 SYS_DMA_CSR_CH2 SYS_DMA_CSSA_L_CH2 SYS_DMA_CSSA_U_CH2 SYS_DMA_CDSA_L_CH2 SYS_DMA_CDSA_U_CH2 SYS_DMA_CEN_CH2 SYS_DMA_CFN_CH2 SYS_DMA_CFI_CH2 SYS_DMA_CEI_CH2 SYS_DMA_CPC_CH2 SYS_DMA_CSDP_CH1 SYS_DMA_CCR_CH1 SYS_DMA_CICR_CH1 SYS_DMA_CSR_CH1 SYS_DMA_CSSA_L_CH1 SYS_DMA_CSSA_U_CH1 SYS_DMA_CDSA_L_CH1 SYS_DMA_CDSA_U_CH1 SYS_DMA_CEN_CH1 SYS_DMA_CFN_CH1 SYS_DMA_CFI_CH1 SYS_DMA_CEI_CH1 SYS_DMA_CPC_CH1 REGISTER NAME SYS_DMA_CSDP_CH0 SYS_DMA_CCR_CH0 SYS_DMA_CICR_CH0 SYS_DMA_CSR_CH0 SYS_DMA_CSSA_L_CH0 SYS_DMA_CSSA_U_CH0 SYS_DMA_CDSA_L_CH0 SYS_DMA_CDSA_U_CH0 SYS_DMA_CEN_CH0 SYS_DMA_CFN_CH0 SYS_DMA_CFI_CH0 SYS_DMA_CEI_CH0 SYS_DMA_CPC_CH0 DESCRIPTION Channel 0 Source/Destination Parameters Register Channel 0 Control Register Channel 0 Interrupt Control Register Channel 0 Status Register Channel 0 Source Start Address Register LSB Channel 0 Source Start Address Register MSB Channel 0 Destination Start Address Register LSB Channel 0 Destination Start Address Register MSB Channel 0 Element Number Register Channel 0 Frame Number Register Channel 0 Frame Index Register Channel 0 Element Index Register Channel 0 Progress Counter Register Reserved Channel 1 Source/Destination Parameters Register Channel 1 Control Register Channel 1 Interrupt Control Register Channel 1 Status Register Channel 1 Source Start Address Register LSB Channel 1 Source Start Address Register MSB Channel 1 Destination Start Address Register LSB Channel 1 Destination Start Address Register MSB Channel 1 Element Number Register Channel 1 Frame Number Register Channel 1 Frame Index Register Channel 1 Element Index Register Channel 1 Progress Counter Register Reserved Channel 2 Source/Destination Parameters Register Channel 2 Control Register Channel 2 Interrupt Control Register Channel 2 Status Register Channel 2 Source Start Address Register LSB Channel 2 Source Start Address Register MSB Channel 2 Destination Start Address Register LSB Channel 2 Destination Start Address Register MSB Channel 2 Element Number Register Channel 2 Frame Number Register Channel 2 Frame Index Register Channel 2 Element Index Register Channel 2 Progress Counter Register 16 16 16 16 16 16 16 16 16 16 16 16 16 RW RW RW R RW RW RW RW RW RW RW RW RW 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef undef 16 16 16 16 16 16 16 16 16 16 16 16 16 RW RW RW R RW RW RW RW RW RW RW RW RW 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef undef ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE RW RW RW R RW RW RW RW RW RW RW RW RW RESET VALUE 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef undef August 2002 - Revised August 2004 SPRS197D 75 Functional Overview Table 3-20. System DMA Controller Registers (Continued) BYTE ADDRESS FFFE:D89A - FFFE:D8BE FFFE:D8C0 FFFE:D8C2 FFFE:D8C4 FFFE:D8C6 FFFE:D8C8 FFFE:D8CA FFFE:D8CC FFFE:D8CE FFFE:D8D0 FFFE:D8D2 FFFE:D8D4 FFFE:D8D6 FFFE:D8D8 FFFE:D8DA - FFFE:D8FE FFFE:D900 FFFE:D902 FFFE:D904 FFFE:D906 FFFE:D908 FFFE:D90A FFFE:D90C FFFE:D90E FFFE:D910 FFFE:D912 FFFE:D914 FFFE:D916 FFFE:D918 FFFE:D91A - FFFE:D93E FFFE:D940 FFFE:D942 FFFE:D944 FFFE:D946 FFFE:D948 FFFE:D94A FFFE:D94C FFFE:D94E FFFE:D950 FFFE:D952 FFFE:D954 FFFE:D956 SYS_DMA_CSDP_CH5 SYS_DMA_CCR_CH5 SYS_DMA_CICR_CH5 SYS_DMA_CSR_CH5 SYS_DMA_CSSA_L_CH5 SYS_DMA_CSSA_U_CH5 SYS_DMA_CDSA_L_CH5 SYS_DMA_CDSA_U_CH5 SYS_DMA_CEN_CH5 SYS_DMA_CFN_CH5 SYS_DMA_CFI_CH5 SYS_DMA_CEI_CH5 SYS_DMA_CSDP_CH4 SYS_DMA_CCR_CH4 SYS_DMA_CICR_CH4 SYS_DMA_CSR_CH4 SYS_DMA_CSSA_L_CH4 SYS_DMA_CSSA_U_CH4 SYS_DMA_CDSA_L_CH4 SYS_DMA_CDSA_U_CH4 SYS_DMA_CEN_CH4 SYS_DMA_CFN_CH4 SYS_DMA_CFI_CH4 SYS_DMA_CEI_CH4 SYS_DMA_CPC_CH4 SYS_DMA_CSDP_CH3 SYS_DMA_CCR_CH3 SYS_DMA_CICR_CH3 SYS_DMA_CSR_CH3 SYS_DMA_CSSA_L_CH3 SYS_DMA_CSSA_U_CH3 SYS_DMA_CDSA_L_CH3 SYS_DMA_CDSA_U_CH3 SYS_DMA_CEN_CH3 SYS_DMA_CFN_CH3 SYS_DMA_CFI_CH3 SYS_DMA_CEI_CH3 SYS_DMA_CPC_CH3 REGISTER NAME Reserved Channel 3 Source/Destination Parameters Register Channel 3 Control Register Channel 3 Interrupt Control Register Channel 3 Status Register Channel 3 Source Start Address Register LSB Channel 3 Source Start Address Register MSB Channel 3 Destination Start Address Register LSB Channel 3 Destination Start Address Register MSB Channel 3 Element Number Register Channel 3 Frame Number Register Channel 3 Frame Index Register Channel 3 Element Index Register Channel 3 Progress Counter Register Reserved Channel 4 Source/Destination Parameters Register Channel 4 Control Register Channel 4 Interrupt Control Register Channel 4 Status Register Channel 4 Source Start Address Register LSB Channel 4 Source Start Address Register MSB Channel 4 Destination Start Address Register LSB Channel 4 Destination Start Address Register MSB Channel 4 Element Number Register Channel 4 Frame Number Register Channel 4 Frame Index Register Channel 4 Element Index Register Channel 4 Progress Counter Register Reserved Channel 5 Source/Destination Parameters Register Channel 5 Control Register Channel 5 Interrupt Control Register Channel 5 Status Register Channel 5 Source Start Address Register LSB Channel 5 Source Start Address Register MSB Channel 5 Destination Start Address Register LSB Channel 5 Destination Start Address Register MSB Channel 5 Element Number Register Channel 5 Frame Number Register Channel 5 Frame Index Register Channel 5 Element Index Register 16 16 16 16 16 16 16 16 16 16 16 16 RW RW RW R RW RW RW RW RW RW RW RW 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef 16 16 16 16 16 16 16 16 16 16 16 16 16 RW RW RW R RW RW RW RW RW RW RW RW RW 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef undef 16 16 16 16 16 16 16 16 16 16 16 16 16 RW RW RW R RW RW RW RW RW RW RW RW RW 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef undef DESCRIPTION ACCESS ACCESS WIDTH TYPE RESET VALUE 76 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-20. System DMA Controller Registers (Continued) BYTE ADDRESS FFFE:D958 FFFE:D95A - FFFE:D97E FFFE:D980 FFFE:D982 FFFE:D984 FFFE:D986 FFFE:D988 FFFE:D98A FFFE:D98C FFFE:D98E FFFE:D990 FFFE:D992 FFFE:D994 FFFE:D996 FFFE:D998 FFFE:D99A - FFFE:D9BE FFFE:D9C0 FFFE:D9C2 FFFE:D9C4 FFFE:D9C6 FFFE:D9C8 FFFE:D9CA FFFE:D9CC FFFE:D9CE FFFE:D9D0 FFFE:D9D2 FFFE:D9D4 FFFE:D9D6 FFFE:D9D8 FFFE:D9DA - FFFE:D9FE FFFE:DA00 FFFE:DA02 FFFE:DA04 FFFE:DA06 FFFE:DA08 FFFE:DA0A FFFE:DA0C FFFE:DA0E FFFE:DA10 FFFE:DA12 FFFE:DA14 SYS_DMA_CSDP_CH8 SYS_DMA_CCR_CH8 SYS_DMA_CICR_CH8 SYS_DMA_CSR_CH8 SYS_DMA_CSSA_L_CH8 SYS_DMA_CSSA_U_CH8 SYS_DMA_CDSA_L_CH8 SYS_DMA_CDSA_U_CH8 SYS_DMA_CEN_CH8 SYS_DMA_CFN_CH8 SYS_DMA_CFI_CH8 SYS_DMA_CSDP_CH7 SYS_DMA_CCR_CH7 SYS_DMA_CICR_CH7 SYS_DMA_CSR_CH7 SYS_DMA_CSSA_L_CH7 SYS_DMA_CSSA_U_CH7 SYS_DMA_CDSA_L_CH7 SYS_DMA_CDSA_U_CH7 SYS_DMA_CEN_CH7 SYS_DMA_CFN_CH7 SYS_DMA_CFI_CH7 SYS_DMA_CEI_CH7 SYS_DMA_CPC_CH7 SYS_DMA_CSDP_CH6 SYS_DMA_CCR_CH6 SYS_DMA_CICR_CH6 SYS_DMA_CSR_CH6 SYS_DMA_CSSA_L_CH6 SYS_DMA_CSSA_U_CH6 SYS_DMA_CDSA_L_CH6 SYS_DMA_CDSA_U_CH6 SYS_DMA_CEN_CH6 SYS_DMA_CFN_CH6 SYS_DMA_CFI_CH6 SYS_DMA_CEI_CH6 SYS_DMA_CPC_CH6 REGISTER NAME SYS_DMA_CPC_CH5 DESCRIPTION Channel 5 Progress Counter Register Reserved Channel 6 Source/Destination Parameters Register Channel 6 Control Register Channel 6 Interrupt Control Register Channel 6 Status Register Channel 6 Source Start Address Register LSB Channel 6 Source Start Address Register MSB Channel 6 Destination Start Address Register LSB Channel 6 Destination Start Address Register MSB Channel 6 Element Number Register Channel 6 Frame Number Register Channel 6 Frame Index Register Channel 6 Element Index Register Channel 6 Progress Counter Register Reserved Channel 7 Source/Destination Parameters Register Channel 7 Control Register Channel 7 Interrupt Control Register Channel 7 Status Register Channel 7 Source Start Address Register LSB Channel 7 Source Start Address Register MSB Channel 7 Destination Start Address Register LSB Channel 7 Destination Start Address Register MSB Channel 7 Element Number Register Channel 7 Frame Number Register Channel 7 Frame Index Register Channel 7 Element Index Register Channel 7 Progress Counter Register Reserved Channel 8 Source/Destination Parameters Register Channel 8 Control Register Channel 8 Interrupt Control Register Channel 8 Status Register Channel 8 Source Start Address Register LSB Channel 8 Source Start Address Register MSB Channel 8 Destination Start Address Register LSB Channel 8 Destination Start Address Register MSB Channel 8 Element Number Register Channel 8 Frame Number Register Channel 8 Frame Index Register 16 16 16 16 16 16 16 16 16 16 16 RW RW RW R RW RW RW RW RW RW RW 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef 16 16 16 16 16 16 16 16 16 16 16 16 16 RW RW RW R RW RW RW RW RW RW RW RW RW 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef undef 16 16 16 16 16 16 16 16 16 16 16 16 16 RW RW RW R RW RW RW RW RW RW RW RW RW 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef undef ACCESS ACCESS WIDTH TYPE 16 RW RESET VALUE undef August 2002 - Revised August 2004 SPRS197D 77 Functional Overview Table 3-20. System DMA Controller Registers (Continued) BYTE ADDRESS FFFE:DA16 FFFE:DA18 FFFE:DA1A - FFFE:DAFE FFFE:DB00 FFFE:DB02 FFFE:DB04 FFFE:DB06 FFFE:DB08 FFFE:DB0A FFFE:DB0C FFFE:DB0E FFFE:DB10 FFFE:DB12 - FFFE:DBFE FFFE:DC00 SYS_DMA_GCR SYS_DMA_LCD_CTRL SYS_DMA_LCD_TOP_F1_L SYS_DMA_LCD_TOP_F1_U SYS_DMA_LCD_BOT_F1_L SYS_DMA_LCD_BOT_F1_U SYS_DMA_LCD_TOP_F2_L SYS_DMA_LCD_TOP_F2_U SYS_DMA_LCD_BOT_F2_L SYS_DMA_LCD_BOT_F2_U REGISTER NAME SYS_DMA_CEI_CH8 SYS_DMA_CPC_CH8 DESCRIPTION Channel 8 Element Index Register Channel 8 Progress Counter Register Reserved LCD Channel Control Register LCD Channel Top Address Frame Buffer 1 Register LSB LCD Channel Top Address Frame Buffer 1 Register MSB LCD Channel Bottom Address Frame Buffer 1 Register LSB LCD Channel Bottom Address Frame Buffer 1 Register MSB LCD Channel Top Address Frame Buffer 2 Register LSB LCD Channel Top Address Frame Buffer 2 Register MSB LCD Channel Bottom Address Frame Buffer 2 Register LSB LCD Channel Bottom Address Frame Buffer 2 Register MSB Reserved DMA Global Control Register 16 RW 0008h 16 16 16 16 16 16 16 16 16 RW RW RW RW RW RW RW RW RW 0000h undef undef undef undef undef undef undef undef ACCESS ACCESS WIDTH TYPE 16 16 RW RW RESET VALUE undef undef Table 3-21. LCD Controller Registers BYTE ADDRESS FFFE:C000 FFFE:C004 FFFE:C008 FFFE:C00C FFFE:C010 FFFE:C014 REGISTER NAME LCD_CONTROL LCD_TIMING0 LCD_TIMING1 LCD_TIMING2 LCD_STATUS LCD_SUBPANEL DESCRIPTION LCD Control Register LCD Timing 0 Register LCD Timing 1 Register LCD Timing 2 Register LCD Status Register LCD Subpanel Display Register ACCESS WIDTH 32 32 32 32 32 32 ACCESS TYPE RW RW RW RW RW RW RESET VALUE 0x0000 0000 undef 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 78 SPRS197D August 2002 - Revised August 2004 Functional Overview 3.15.2 * MPU Public Peripheral Registers Serial Ports - - - - - - - McBSP2 Registers MICROWIRE Registers I2C Registers HDQ/1-Wire Interface Registers MMC/SD Registers USB Function Registers USB Host Registers Camera Interface Registers MPUIO/Keyboard Registers PWL Registers PWT Registers LED Pulse Generator 1 Registers LED Pulse Generator 2 Registers 32k Timer Registers Real-Time Clock Registers Frame Adjustment Counter Registers The MPU public peripheral registers include the following: * * Parallel Ports - - - - - - Human Interface support * Timers and Counters - - - August 2002 - Revised August 2004 SPRS197D 79 Functional Overview Table 3-22. McBSP2 Registers BYTE ADDRESS FFFB:1000 FFFB:1002 FFFB:1004 FFFB:1006 FFFB:1008 FFFB:100A FFFB:100C FFFB:100E FFFB:1010 FFFB:1012 FFFB:1014 FFFB:1016 FFFB:1018 FFFB:101A FFFB:101C FFFB:101E FFFB:1020 FFFB:1022 FFFB:1024 FFFB:1026 FFFB:1028 FFFB:102A FFFB:102C FFFB:102E FFFB:1030 FFFB:1032 FFFB:1034 FFFB:1036 FFFB:1038 FFFB:103A FFFB:103C REGISTER NAME MCBSP2_DRR2 MCBSP2_DRR1 MCBSP2_DXR2 MCBSP2_DXR1 MCBSP2_SPCR2 MCBSP2_SPCR1 MCBSP2_RCR2 MCBSP2_RCR1 MCBSP2_XCR2 MCBSP2_XCR1 MCBSP2_SRGR2 MCBSP2_SRGR1 MCBSP2_MCR2 MCBSP2_MCR1 MCBSP2_RCERA MCBSP2_RCERB MCBSP2_XCERA MCBSP2_XCERB MCBSP2_PCR0 MCBSP2_RCERC MCBSP2_RCERD MCBSP2_XCERC MCBSP2_XCERD MCBSP2_RCERE MCBSP2_RCERF MCBSP2_XCERE MCBSP2_XCERF MCBSP2_RCERG MCBSP2_RCERH MCBSP2_XCERG MCBSP2_XCERH DESCRIPTION McBSP2 Data Receive Register 2 McBSP2 Data Receive Register 1 McBSP2 Data Transmit Register 2 McBSP2 Data Transmit Register 1 McBSP2 Serial Port Control Register 2 McBSP2 Serial Port Control Register 1 McBSP2 Receive Control Register 2 McBSP2 Receive Control Register 1 McBSP2 Transmit Control Register 2 McBSP2 Transmit Control Register 1 McBSP2 Sample Rate Generator Register 2 McBSP2 Sample Rate Generator Register 1 McBSP2 Multichannel Control Register 2 McBSP2 Multichannel Control Register 1 McBSP2 Receive Channel Enable Register Partition A McBSP2 Receive Channel Enable Register Partition B McBSP2 Transmit Channel Enable Register Partition A McBSP2 Transmit Channel Enable Register Partition B McBSP2 Pin Control Register 0 McBSP2 Receive Channel Enable Register Partition C McBSP2 Receive Channel Enable Register Partition D McBSP2 Transmit Channel Enable Register Partition C McBSP2 Transmit Channel Enable Register Partition D McBSP2 Receive Channel Enable Register Partition E McBSP2 Receive Channel Enable Register Partition F McBSP2 Transmit Channel Enable Register Partition E McBSP2 Transmit Channel Enable Register Partition F McBSP2 Receive Channel Enable Register Partition G McBSP2 Receive Channel Enable Register Partition H McBSP2 Transmit Channel Enable Register Partition G McBSP2 Transmit Channel Enable Register Partition H ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 2000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Table 3-23. MICROWIRE Registers BYTE ADDRESS FFFB:3000 FFFB:3000 FFFB:3004 FFFB:3008 FFFB:300C FFFB:3010 FFFB:3014 FFFB:3018 REGISTER NAME TD RD CSR SR1 SR2 SR3 SR4 SR5 DESCRIPTION MICROWIRE Transmit Data Register MICROWIRE Receive Data Register MICROWIRE Control and Status Register MICROWIRE Setup Register 1 MICROWIRE Setup Register 2 MICROWIRE Setup Register 3 MICROWIRE Setup Register 4 MICROWIRE Setup Register 5 ACCESS WIDTH 16 16 16 16 16 16 16 16 ACCESS TYPE W R RW RW RW RW RW RW RESET VALUE undef undef undef undef undef 0000h 0000h 0000h 80 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-24. I2C Registers BYTE ADDRESS FFFB:3800 FFFB:3804 FFFB:3808 FFFB:380C FFFB:3810 FFFB:3814 FFFB:3818 FFFB:381C FFFB:3820 FFFB:3824 FFFB:3828 FFFB:382C FFFB:3830 FFFB:3834 FFFB:3838 FFFB:383C I2C_CON I2C_OA I2C_SA I2C_PSC I2C_SCLL I2C_SCLH I2C_SYSTEST I2C_BUF I2C_CNT I2C_DATA REGISTER NAME I2C_REV I2C_IE I2C_STAT I2C_IV DESCRIPTION I2C Module Version Register I2C Interrupt Enable Register I2C Status Register I2C Interrupt Vector Register Reserved I2C Buffer Configuration Register I2C Data Counter Register I2C Data Access Register Reserved I2C Configuration Register I2C Own Address Register I2C Slave Address Register I2C Clock Prescaler Register I2C SCL Low Timer Register I2C SCL High Timer Register I2C System Test Register 16 16 16 16 16 16 16 RW RW RW RW RW RW RW 0000h 0000h 03FFh 0000h 0000h 0000h 0000h 16 16 16 RW RW RW 0000h 0000h 0000h ACCESS WIDTH 16 16 16 16 ACCESS TYPE RW RW R R RESET VALUE 0011h 0000h 0000h 0000h Table 3-25. HDQ/1-Wire Interface Registers BYTE ADDRESS FFFB:C000 FFFB:C004 FFFB:C008 FFFB:C00C REGISTER NAME TXR RXR CSR ISR TX Write Data Register RX Receive Buffer Register Control and Status Register Interrupt Status Register DESCRIPTION ACCESS WIDTH 8 8 8 8 ACCESS TYPE RW R RW RW RESET VALUE 00h undef 00h 00h August 2002 - Revised August 2004 SPRS197D 81 Functional Overview Table 3-26. MMC/SD Registers BYTE ADDRESS FFFB:7800 FFFB:7804 FFFB:7808 FFFB:780C FFFB:7810 FFFB:7814 FFFB:7818 FFFB:781C FFFB:7820 FFFB:7824 FFFB:7828 FFFB:782C FFFB:7834 FFFB:7838 FFFB:783C FFFB:7840 FFFB:7844 FFFB:7848 FFFB:784C FFFB:7850 FFFB:7854 FFFB:7858 FFFB:785C REGISTER NAME MMC_CMD MMC_ARGL MMC_ARGH MMC_CON MMC_STAT MMC_IE MMC_CTO MMC_DTO MMC_DATA MMC_BLEN MMC_NBLK MMC_BUF MMC_SDIO MMC_SYST MMC_REV MMC_RSP0 MMC_RSP1 MMC_RSP2 MMC_RSP3 MMC_RSP4 MMC_RSP5 MMC_RSP6 MMC_RSP7 MMC Command MMC Argument Low MMC Argument High MMC System Configuration MMC Status MMC System Interrupt Enable MMC Command Timeout MMC Data Timeout MMC TX/RX FIFO Data MMC Block Length MMC Number Of Blocks MMC Buffer Configuration MMC SDIO Mode Configuration MMC System Test MMC Module Version MMC Command Response 0 MMC Command Response 1 MMC Command Response 2 MMC Command Response 3 MMC Command Response 4 MMC Command Response 5 MMC Command Response 6 MMC Command Response 7 DESCRIPTION ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R R R R R R R R RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 1F00h 0000h 2000h - undef undef undef undef undef undef undef undef 82 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-27. USB Function Registers BYTE ADDRESS FFFB:4000 FFFB:4004 FFFB:4008 FFFB:400C FFFB:4010 FFFB:4014 FFFB:4018 FFFB:401C FFFB:4020 FFFB:4024 FFFB:4028 FFFB:402C FFFB:4030 FFFB:4034 FFFB:4038 FFFB:403C FFFB:4040 FFFB:4044 FFFB:4048 FFFB:404C FFFB:4050 FFFB:4054 FFFB:4058 FFFB:405C FFFB:4060 FFFB:4064 FFFB:4068 FFFB:406C - FFFB:407C FFFB:4080 FFFB:4084 FFFB:4088 FFFB:408C FFFB:4090 FFFB:4094 FFFB:4098 FFFB:409C FFFB:40A0 FFFB:40A4 FFFB:40A8 FFFB:40AC FFFB:40B0 FFFB:40B4 FFFB:40B8 EP0 EP1_RX EP2_RX EP3_RX EP4_RX EP5_RX EP6_RX EP7_RX EP8_RX EP9_RX EP10_RX EP11_RX EP12_RX EP13_RX EP14_RX RXDMA0 RXDMA1 RXDMA2 TXDMA0 TXDMA1 TXDMA2 RXDMA_CFG TXDMA_CFG DATA_DMA REGISTER NAME REV EP_NUM DATA CTRL STAT_FLG RXFSTAT SYSCON1 SYSCON2 DEVSTAT SOF IRQ_EN DMA_IRQ_EN IRQ_SRC EPN_STAT DMAN_STAT Revision Register Endpoint Selection Register Data Register Control Register Status Flag Register Receive FIFO Status Register System Configuration 1 Register System Configuration 2 Register Device Status Register Start of Frame Register Interrupt Enable Register DMA Interrupt Enable Register Interrupt Source Register Endpoint Interrupt Status Register DMA Endpoint Interrupt Status Register Reserved Receive Channels DMA Configuration Register Transmit Channels DMA Configuration Register DMA FIFO Data Register Reserved Transmit DMA Control 0 Register Transmit DMA Control 1 Register Transmit DMA Control 2 Register Reserved Receive DMA Control 0 Register Receive DMA Control 1 Register Receive DMA Control 2 Register Reserved Endpoint Configuration 0 Register Receive Endpoint Configuration 1 Register Receive Endpoint Configuration 2 Register Receive Endpoint Configuration 3 Register Receive Endpoint Configuration 4 Register Receive Endpoint Configuration 5 Register Receive Endpoint Configuration 6 Register Receive Endpoint Configuration 7 Register Receive Endpoint Configuration 8 Register Receive Endpoint Configuration 9 Register Receive Endpoint Configuration 10 Register Receive Endpoint Configuration 11 Register Receive Endpoint Configuration 12 Register Receive Endpoint Configuration 13 Register Receive Endpoint Configuration 14 Register 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0000h undef undef undef undef undef undef undef undef undef undef undef undef undef undef 16 16 16 RW RW RW 0000h 0000h 0000h 16 16 16 RW RW RW 0000h 0000h 0000h 16 16 16 RW RW RW 0000h 0000h undef DESCRIPTION ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE R RW RW RW R R RW RW R R RW RW RW R R RESET VALUE - 0000h undef 0000h 0202h 0000h 0000h 0000h undef 0000h undef undef 0000h 0000h 0000h August 2002 - Revised August 2004 SPRS197D 83 Functional Overview Table 3-27. USB Function Registers (Continued) BYTE ADDRESS FFFB:40BC FFFB:40C0 FFFB:40C4 FFFB:40C8 FFFB:40CC FFFB:40D0 FFFB:40D4 FFFB:40D8 FFFB:40DC FFFB:40E0 FFFB:40E4 FFFB:40E8 FFFB:40EC FFFB:40F0 FFFB:40F4 FFFB:40F8 FFFB:40FC EP1_TX EP2_TX EP3_TX EP4_TX EP5_TX EP6_TX EP7_TX EP8_TX EP9_TX EP10_TX EP11_TX EP12_TX EP13_TX EP14_TX EP15_TX REGISTER NAME EP15_RX DESCRIPTION Receive Endpoint Configuration 15 Register Reserved Transmit Endpoint Configuration 1 Register Transmit Endpoint Configuration 2 Register Transmit Endpoint Configuration 3 Register Transmit Endpoint Configuration 4 Register Transmit Endpoint Configuration 5 Register Transmit Endpoint Configuration 6 Register Transmit Endpoint Configuration 7 Register Transmit Endpoint Configuration 8 Register Transmit Endpoint Configuration 9 Register Transmit Endpoint Configuration 10 Register Transmit Endpoint Configuration 11 Register Transmit Endpoint Configuration 12 Register Transmit Endpoint Configuration 13 Register Transmit Endpoint Configuration 14 Register Transmit Endpoint Configuration 15 Register 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW undef undef undef undef undef undef undef undef undef undef undef undef undef undef undef ACCESS WIDTH 16 ACCESS TYPE RW RESET VALUE undef 84 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-28. USB Host Controller Registers BYTE ADDRESS FFFB:A000 FFFB:A004 FFFB:A008 FFFB:A00C FFFB:A010 FFFB:A014 FFFB:A018 FFFB:A01C FFFB:A020 FFFB:A024 FFFB:A028 FFFB:A02C FFFB:A030 FFFB:A034 FFFB:A038 FFFB:A03C FFFB:A040 FFFB:A044 FFFB:A048 FFFB:A04C FFFB:A050 FFFB:A054 FFFB:A058 FFFB:A05C FFFB:A060 - FFFB:A0DC FFFB:A0E0 FFFB:A0E4 FFFB:A0E8 FFFB:A0EC HostUEAddr HostUEStatus HostTimeoutCtrl HostRevision REGISTER NAME HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcFmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 HcRhPortStatus2 HcRhPortStatus3 DESCRIPTION OHCI Revision Register Host Controller Operating Mode Register Host Controller Command and Status Register Host Controller Interrupt Status Register Host Controller Interrupt Enable Register Host Controller Interrupt Disable Register LB Virtual Address HCCA Register LB Virtual Address Current Periodic EP Descriptor Register LB Virtual Address Control EP Descriptor List Head Register LB Virtual Address Current Control EP Descriptor Register LB Virtual Address Bulk EP Descriptor List Head Register LB Virtual Address Current Bulk EP Descriptor Register LB Virtual Address Retired Transfer Descriptor List Head Register Frame Interval Register Remaining Frame Time Register Remaining Frame Number Register Periodic Start Time Register Low Speed Start Threshold Register USB Root Hub Descriptor Register A USB Root Hub Descriptor Register B USB Root Hub Status Register Port 1 Control and Status Register Port 2 Control and Status Register Port 3 Control and Status Register Reserved LB Virtual Address Last Unrecoverable Error Register LB Cycle Type Last Unrecoverable Error Register USB Host Mastered Local Bus Time-out Enable Register USB Host Controller Revision Register 32 32 32 32 R R RW R 0000 0000h 0000 0000h 0000 0000h - ACCESS WIDTH 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 ACCESS TYPE R RW RW RW RW R RW RW RW RW RW RW R RW R R RW RW RW RW RW RW RW RW RESET VALUE 0000 0010h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h undef 0000 2EDFh 0000 0000h 0000 0000h 0000 0000h 0000 0628h 0A00 1203h 0000 0000h 0000 0000h 0000 0100h 0000 0100h 0000 0100h Table 3-29. Camera Interface Registers BYTE ADDRESS FFFB:6800 FFFB:6804 FFFB:6808 FFFB:680C FFFB:6810 FFFB:6814 FFFB:6818 REGISTER NAME CTRLCLOCK IT_STATUS MODE STATUS CAMDATA GPIO PEAK_COUNTER Clock Control Register Interrupt Status Register Mode Configuration Register Status Register Image Data Register GPIO Register Fifo Peak Counter Register DESCRIPTION ACCESS WIDTH 32 32 32 32 32 32 32 ACCESS TYPE RW R RW R R RW RW RESET VALUE 0000 0000h 0000 0000h 0000 0200h 0000 0000h 0000 0000h 0000 0000h 0000 0000h August 2002 - Revised August 2004 SPRS197D 85 Functional Overview Table 3-30. MPU I/O/Keyboard Registers BYTE ADDRESS FFFB:5000 FFFB:5004 FFFB:5008 FFFB:500C FFFB:5010 FFFB:5014 FFFB:5018 FFFB:501C FFFB:5020 FFFB:5024 FFFB:5028 FFFB:502C FFFB:5030 FFFB:5034 KBR_LATCH KBC_REG GPIO_EVENT_MODE GPIO_INT_EDGE KBD_INT GPIO_INT KBD_MASKIT GPIO_MASKIT GPIO_DEBOUNCING GPIO_LATCH REGISTER NAME INPUT_LATCH OUTPUT_REG IO_CNTL Input Register Output Register Input Output Control Register Reserved Keyboard Row Inputs Register Keyboard Column Outputs Register GPIO Event Mode Register GPIO Interrupt Edge Register Keyboard Interrupt Register GPIO Interrupt Register Keyboard Mask Interrupt Register GPIO Mask Interrupt Register GPIO Debouncing Register GPIO Latch Register 16 16 16 16 16 16 16 16 16 16 R RW RW RW R R RW RW RW R undef 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h DESCRIPTION ACCESS WIDTH 16 16 16 ACCESS TYPE R RW RW RESET VALUE undef undef FFFFh Table 3-31. PWL Registers BYTE ADDRESS FFFB:5800 FFFB:5804 REGISTER NAME PWL_LEVEL PWL_CTRL PWL Level Register PWL Control Register DESCRIPTION ACCESS WIDTH 8 8 ACCESS TYPE RW RW RESET VALUE 0000h 0000h Table 3-32. PWT Registers BYTE ADDRESS FFFB:6000 FFFB:6004 FFFB:6008 REGISTER NAME PWT_FRC PWT_VCR PWT_GCR DESCRIPTION PWT Frequency Control Register PWT Volume Control Register PWT General Control Register ACCESS WIDTH 8 8 8 ACCESS TYPE RW RW RW RESET VALUE 0000h 0000h 0000h Table 3-33. LED Pulse Generator 1 Registers BYTE ADDRESS FFFB:D000 FFFB:D004 REGISTER NAME LCR_1 PMR_1 LPG1 Control Register LPG1 Power Management Register DESCRIPTION ACCESS WIDTH 8 8 ACCESS TYPE RW RW RESET VALUE 00h 00h Table 3-34. LED Pulse Generator 2 Registers BYTE ADDRESS FFFB:D800 FFFB:D804 REGISTER NAME LCR_2 PMR_2 LPG2 Control Register LPG2 Power Management Register DESCRIPTION ACCESS WIDTH 8 8 ACCESS TYPE RW RW RESET VALUE 00h 00h Table 3-35. 32k Timer Registers BYTE ADDRESS FFFB:9000 FFFB:9004 FFFB:9008 REGISTER NAME TVR TCR CR Tick Value Register Tick Counter Register Control Register DESCRIPTION ACCESS WIDTH 32 32 32 ACCESS TYPE RW R RW RESET VALUE 00FF FFFFh 00FF FFFFh 0000 0008h 86 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-36. Real-Time Clock Registers BYTE ADDRESS FFFB:4800 FFFB:4804 FFFB:4808 FFFB:480C FFFB:4810 FFFB:4814 FFFB:4818 FFFB:481C FFFB:4820 FFFB:4824 FFFB:4828 FFFB:482C FFFB:4830 FFFB:4834 FFFB:4838 - FFFB:483C FFFB:4840 FFFB:4844 FFFB:4848 FFFB:484C FFFB:4850 RTC_CTRL_REG RTC_STATUS_REG RTC_INTERRUPTS_REG RTC_COMP_LSB_REG RTC_COMP_MSB_REG ALARM_SECOND_REG ALARM_MINUTES_REG ALARM_HOURS_REG ALARM_DAYS_REG ALARM_MONTHS_REG ALARM_YEARS_REG REGISTER NAME SECONDS_REG MINUTES_REG HOURS_REG DAYS_REG MONTHS_REG YEARS_REG WEEK_REG DESCRIPTION RTC Seconds Register RTC Minutes Register RTC Hours Register RTC Days Register RTC Months Register RTC Years Register RTC Day of the Week Register Reserved RTC Alarm Seconds Register RTC Alarm Minutes Register RTC Alarm Hours Register RTC Alarm Days Register RTC Alarm Months Register RTC Alarm Years Register Reserved RTC Control Register RTC Status Register RTC Interrupts Register RTC Compensation LSB Register RTC Compensation MSB Register 8 8 8 8 8 RW RW RW RW RW 00h 00h 00h 00h 00h 8 8 8 8 8 8 RW RW RW RW RW RW 00h 00h 00h 01h 01h 00h ACCESS WIDTH 8 8 8 8 8 8 8 ACCESS TYPE RW RW RW RW RW RW RW RESET VALUE 00h 00h 00h 01h 01h 00h 00h Table 3-37. Frame Adjustment Counter Registers BYTE ADDRESS FFFB:A800 FFFB:A804 FFFB:A808 FFFB:A80C FFFB:A810 FFFB:A814 REGISTER NAME FARC FSC CTRL STATUS SYNC_CNT START_CNT DESCRIPTION Frame Adjustment Reference Count Register Frame Start Count Register Control and Configuration Register Status Register Frame Synchronization Register Frame Start Counter Register ACCESS WIDTH 16 16 16 16 16 16 ACCESS TYPE RW R RW R R R RESET VALUE 0000h 0000h 0000h 0000h undef undef August 2002 - Revised August 2004 SPRS197D 87 Functional Overview 3.15.3 * * MPU Configuration Registers Pin Multiplexing Setup: - - - - OMAP5910 Pin Configuration Registers Local Bus Control Registers Local Bus MMU Registers DSP MMU Registers MPU Interface (MPUI) Registers TIPB (Private) Bridge 1 Configuration Registers TIPB (Public) Bridge 2 Configuration Registers MPU UART TI Peripheral Bus Switch Registers Traffic Controller Registers MPU Clock/Reset/Power Mode Control Registers DPLL1 Configuration Register Ultra Low-Power Device Module Registers Device Die Identification Registers JTAG Identification Code Register Local Bus and MMU Setup: The MPU Configuration Registers include the following: * MPUI and TIPB Setup: - - - - - * Clock and Power Management: - - - * Device Identification: - - 88 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-38. OMAP 5910 Pin Configuration Registers BYTE ADDRESS FFFE:1000 FFFE:1004 FFFE:1008 FFFE:100C FFFE:1010 FFFE:1014 FFFE:1018 FFFE:101C FFFE:1020 FFFE:1024 FFFE:1028 FFFE:102C FFFE:1030 FFFE:1034 FFFE:1038 FFFE:103C FFFE:1040 FFFE:1044 FFFE:1048 FFFE:104C FFFE:1050 FFFE:1054 - FFFE:105C FFFE:1060 FFFE:1064 - FFFE:106C FFFE:1070 FFFE:1074 - FFFE:107C FFFE:1080 MOD_CONF_CTRL_0 TEST_DBG_CTRL_0 VOLTAGE_CTRL_0 PULL_DWN_CTRL_0 PULL_DWN_CTRL_1 PULL_DWN_CTRL_2 PULL_DWN_CTRL_3 GATE_INH_CTRL_0 REGISTER NAME FUNC_MUX_CTRL_0 FUNC_MUX_CTRL_1 FUNC_MUX_CTRL_2 COMP_MODE_CTRL_0 FUNC_MUX_CTRL_3 FUNC_MUX_CTRL_4 FUNC_MUX_CTRL_5 FUNC_MUX_CTRL_6 FUNC_MUX_CTRL_7 FUNC_MUX_CTRL_8 FUNC_MUX_CTRL_9 FUNC_MUX_CTRL_A FUNC_MUX_CTRL_B FUNC_MUX_CTRL_C FUNC_MUX_CTRL_D DESCRIPTION Functional Multiplexing Control 0 Register Functional Multiplexing Control 1 Register Functional Multiplexing Control 2 Register Compatibility Mode Control 0 Register Functional Multiplexing Control 3 Register Functional Multiplexing Control 4 Register Functional Multiplexing Control 5 Register Functional Multiplexing Control 6 Register Functional Multiplexing Control 7 Register Functional Multiplexing Control 8 Register Functional Multiplexing Control 9 Register Functional Multiplexing Control A Register Functional Multiplexing Control B Register Functional Multiplexing Control C Register Functional Multiplexing Control D Register Reserved Pulldown Control 0 Register Pulldown Control 1 Register Pulldown Control 2 Register Pulldown Control 3 Register Gate and Inhibit Control 0 Register Reserved Voltage Control 0 Register Reserved Test Debug Control 0 Register Reserved Module Configuration Control 0 Register 32 RW 0000 0000h 32 RW 0000 0000h 32 RW 0000 0000h 32 32 32 32 32 RW RW RW RW RW 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h ACCESS WIDTH 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 ACCESS TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RESET VALUE 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h Table 3-39. Local Bus Control Registers BYTE ADDRESS FFFE:C100 FFFE:C104 FFFE:C108 FFFE:C10C FFFE:C110 FFFE:C114 FFFE:C118 FFFE:C11C FFFE:C120 REGISTER NAME LB_MPU_TIMEOUT LB_HOLD_TIMER LB_PRIORITY_REG LB_CLOCK_DIV LB_ABORT_ADD LB_ABORT_DATA LB_ABORT_STATUS LB_IRQ_OUTPUT LB_IRQ_INPUT DESCRIPTION Local Bus MPU Access TIMEOUT Local Bus Hold Timer Local Bus MPU Access Priority Local Bus Clock Divider Local Bus Address Of Aborted MPU Cycle Local Bus Cycle Data Of Aborted MPU Write Cycle Local Bus Cycle Type Of Aborted MPU Write Cycle LocaL Bus External Interrupt Output Control Local Bus External Interrupt Status ACCESS WIDTH 32 32 32 32 32 32 32 32 32 ACCESS TYPE RW RW RW RW R R R RW RW RESET VALUE 0000 00FFh 0000 0000h 0000 0000h 0000 00FCh FFFF FFFFh FFFF FFFFh 0000 0000h 0000 0000h 0000 0000h August 2002 - Revised August 2004 SPRS197D 89 Functional Overview Table 3-40. Local Bus MMU Registers BYTE ADDRESS FFFE:C204 FFFE:C208 FFFE:C20C FFFE:C210 FFFE:C214 FFFE:C218 FFFE:C21C FFFE:C220 FFFE:C224 FFFE:C228 FFFE:C22C FFFE:C230 FFFE:C234 FFFE:C238 FFFE:C23C FFFE:C240 FFFE:C244 FFFE:C248 FFFE:C24C REGISTER NAME LB_MMU_WALKING_ST_REG LB_MMU_CNTL_REG LB_MMU_FAULT_AD_H_REG LB_MMU_FAULT_AD_L_REG LB_MMU_FAULT_ST_REG LB_MMU_IT_ACK_REG LB_MMU_TTB_H_REG LB_MMU_TTB_L_REG LB_MMU_LOCK_REG LB_MMU_LD_TLB_REG LB_MMU_CAM_H_REG LB_MMU_CAM_L_REG LB_MMU_RAM_H_REG LB_MMU_RAM_L_REG LB_MMU_GFLUSH_REG LB_MMU_FLUSH_ENTRY_REG LB_MMU_READ_CAM_H_REG LB_MMU_READ_CAM_L_REG LB_MMU_READ_RAM_H_REG DESCRIPTION Local Bus MMU Walking Status Local Bus MMU Control Local Bus MMU Fault Address High Local Bus MMU Fault Address Low Local Bus MMU Fault Status Local Bus MMU Interrupt Acknowledge Local Bus MMU TTB Register High Local Bus MMU TTB Register Low Local Bus MMU Lock Counter Local Bus MMU TLB Load/Read Control Local Bus MMU CAM Entry High Local Bus MMU CAM Entry Low Local Bus MMU RAM Entry High Local Bus MMU RAM Entry Low Local Bus MMU Global Flush Control Local Bus MMU Individual Entry Flush Control Local Bus MMU CAM Read High Local Bus MMU CAM Read Low Local Bus MMU RAM Read High Local Bus MMU RAM Read Low ACCESS WIDTH 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 ACCESS TYPE RW RW R R R W RW RW RW RW RW RW RW RW RW RW RW RW RW RW RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h FFFE:C250 LB_MMU_READ_RAM_L_REG Write access in ARM supervisor mode only. 90 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-41. DSP MMU Registers BYTE ADDRESS FFFE:D200 FFFE:D204 FFFE:D208 FFFE:D20C FFFE:D210 FFFE:D214 FFFE:D218 FFFE:D21C FFFE:D220 FFFE:D224 FFFE:D228 FFFE:D22C FFFE:D230 FFFE:D234 FFFE:D238 FFFE:D23C FFFE:D240 FFFE:D244 FFFE:D248 FFFE:D24C FFFE:D250 REGISTER NAME DSP_MMU_PREFETCH_REG DSP_MMU_WALKING_ST_REG DSP_MMU_CNTL_REG DSP_MMU_FAULT_AD_H_REG DSP_MMU_FAULT_AD_L_REG DSP_MMU_F_ST_REG DSP_MMU_IT_ACK_REG DSP_MMU_TTB_H_REG DSP_MMU_TTB_L_REG DSP_MMU_LOCK_REG DSP_MMU_LD_TLB_REG DSP_MMU_CAM_H_REG DSP_MMU_CAM_L_REG DSP_MMU_RAM_H_REG DSP_MMU_RAM_L_REG DSP_MMU_GFLUSH_REG DSP_MMU_FLUSH_ENTRY_REG DSP_MMU_READ_CAM_H_REG DSP_MMU_READ_CAM_L_REG DSP_MMU_READ_RAM_H_REG DSP_MMU_READ_RAM_L_REG DESCRIPTION DSP MMU Prefetch Register DSP MMU Prefetch Status Register DSP MMU Control Register DSP MMU Fault Address Register MSB DSP MMU Fault Address Register LSB DSP MMU Fault Status Register DSP MMU IT Acknowledge Register DSP MMU TTB Register MSB DSP MMU TTB Register LSB DSP MMU Lock Counter Register DSP MMU Load Entry TLB Register DSP MMU CAM Entry Register MSB DSP MMU CAM Entry Register LSB DSP MMU RAM Entry Register MSB DSP MMU RAM Entry Register LSB DSP MMU Global Flush Register DSP MMU Individual Flush Register DSP MMU Read CAM Register MSB DSP MMU Read CAM Register LSB DSP MMU Read RAM Register MSB DSP MMU Read RAM Register LSB ACCESS WIDTH 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 ACCESS TYPE RW R RW R R R W RW RW RW RW RW RW RW RW RW RW RW RW RW RW RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Table 3-42. MPUI Registers BYTE ADDRESS FFFE:C900 FFFE:C904 FFFE:C908 FFFE:C90C FFFE:C910 FFFE:C914 FFFE:C918 FFFE:C91C REGISTER NAME CTRL_REG DEBUG_ADDR DEBUG_DATA DEBUG_FLAG STATUS_REG DSP_STATUS_REG DSP_BOOT_CONFIG DSP_MPUI_CONFIG DESCRIPTION MPUI Control Register MPUI Debug Address Register MPUI Debug Data Register MPUI Debug Flag Register MPUI Status Register MPUI DSP Status Register MPUI Boot Configuration Register MPUI DSP MPUI Configuration Register ACCESS WIDTH 32 32 32 32 32 32 32 32 ACCESS TYPE RW R R R R R RW RW RESET VALUE 0003 FF1Bh 01FF FFFFh FFFF FFFFh 0800h 0000h undef 0000h FFFFh Table 3-43. TIPB (Private) Bridge 1 Configuration Registers BYTE ADDRESS FFFE:CA00 FFFE:CA04 FFFE:CA08 FFFE:CA0C FFFE:CA10 FFFE:CA14 FFFE:CA18 FFFE:CA1C REGISTER NAME TIPB_CNTL TIPB_BUS_ALLOC MPU_TIPB_CNTL ENHANCED_TIPB_CNTL ADDRESS_DBG DATA_DEBUG_LOW DATA_DEBUG_HIGH DEBUG_CNTR_SIG DESCRIPTION Private TIPB Control Register Private TIPB Bus Allocation Register Private MPU TIPB Control Register Private Enhanced TIPB Control Register Private Debug Address Register Private Debug Data LSB Register Private Debug Data MSB Register Private Debug Control Signals Register ACCESS WIDTH 32 32 32 32 32 32 32 32 ACCESS TYPE RW RW RW RW R R R R RESET VALUE FF11h 0009h 0000h 0007h FFFFh FFFFh FFFFh 00F8h August 2002 - Revised August 2004 SPRS197D 91 Functional Overview Table 3-44. TIPB (Public) Bridge 2 Configuration Registers BYTE ADDRESS FFFE:D300 FFFE:D304 FFFE:D308 FFFE:D30C FFFE:D310 FFFE:D314 FFFE:D318 FFFE:D31C REGISTER NAME TIPB_CNTL TIPB_BUS_ALLOC MPU_TIPB_CNTL ENHANCED_TIPB_CNTL ADDRESS_DBG DATA_DEBUG_LOW DATA_DEBUG_HIGH DEBUG_CNTR_SIG DESCRIPTION Public TIPB Control Register Public TIPB Bus Allocation Register Public MPU TIPB Control Register Public Enhanced TIPB Control Register Public Debug Address Register Public Debug Data LSB Register Public Debug Data MSB Register Public Debug Control Signals Register ACCESS WIDTH 16 16 16 16 16 16 16 16 ACCESS TYPE RW RW RW RW R R R R RESET VALUE FF11h 0009h 0000h 0007h FFFFh FFFFh FFFFh 00F8h Table 3-45. MPU UART TIPB Bus Switch Registers BYTE ADDRESS FFFB:C800 FFFB:C804 FFFB:C808 - FFFB:C83C FFFB:C840 FFFB:C844 FFFB:C848 - FFFB:C87C FFFB:C880 FFFB:C884 RHSW_ARM_CNF3 RHSW_ARM_STA3 RHSW_ARM_CNF2 RHSW_ARM_STA2 REGISTER NAME RHSW_ARM_CNF1 RHSW_ARM_STA1 DESCRIPTION UART1 TIPB Switch Configuration Register (MPU) UART1 TIPB Switch Status Register (MPU) Reserved UART2 TIPB Switch Configuration Register (MPU) UART2 TIPB Switch Status Register (MPU) Reserved UART3 TIPB Switch Configuration Register (MPU) UART3 TIPB Switch Status Register (MPU) 16 16 RW R 0001h 0001h 16 16 RW R 0001h 0001h ACCESS WIDTH 16 16 ACCESS TYPE RW R RESET VALUE 0001h 0001h 92 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-46. Traffic Controller Registers BYTE ADDRESS FFFE:CC00 FFFE:CC04 FFFE:CC08 FFFE:CC0C FFFE:CC10 FFFE:CC14 FFFE:CC18 FFFE:CC1C FFFE:CC20 FFFE:CC24 FFFE:CC28 FFFE:CC2C FFFE:CC30 FFFE:CC34 FFFE:CC38 FFFE:CC3C EMIFF_SDRAM_CONFIG_2 REGISTER NAME IMIF_PRIO EMIFS_PRIO_REG EMIFF_PRIO_REG EMIFS_CONFIG_REG EMIFS_CS0_CONFIG EMIFS_CS1_CONFIG EMIFS_CS2_CONFIG EMIFS_CS3_CONFIG EMIFF_SDRAM_CONFIG EMIFF_MRS TIMEOUT1 TIMEOUT2 TIMEOUT3 ENDIANISM DESCRIPTION TC IMIF Priority Register TC EMIFS Priority Register TC EMIFF Priority Register TC EMIFS Configuration Register TC EMIFS CS0 Configuration Register TC EMIFS CS1 Configuration Register TC EMIFS CS2 Configuration Register TC EMIFS CS3 Configuration Register TC EMIFF SDRAM Configuration Register TC EMIFF SDRAM MRS Register TC Timeout 1 Register TC Timeout 2 Register TC Timeout 3 Register TC Endianism Register Reserved TC EMIFF SDRAM Configuration Register 2 ACCESS WIDTH 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 ACCESS TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RESET VALUE 0000 0000h 0000 0000h 0000 0000h y00z0b 0010 FFFBh 0010 FFFBh 0010 FFFBh 0010 FFFBh 0061 8800h 0000 0037h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0003h FFFE:CC40 EMIFS_CFG_DYN_WAIT TC EMIFS Wait-State Configuration Register 32 RW 0000 0000h The value of y is dependent upon the state of the FLASH.RDY pin and the value of z is dependent upon the state of the MPU_BOOT pin upon power-on reset. Table 3-47. MPU Clock/Reset/Power Mode Control Registers BYTE ADDRESS FFFE:CE00 FFFE:CE04 FFFE:CE08 FFFE:CE0C FFFE:CE10 FFFE:CE14 FFFE:CE18 REGISTER NAME ARM_CKCTL ARM_IDLECT1 ARM_IDLECT2 ARM_EWUPCT ARM_RSTCT1 ARM_RSTCT2 ARM_SYSST DESCRIPTION MPU Clock Control Register MPU Idle Control 1 Register MPU Idle Control 2 Register MPU External Wakeup Control Register MPU Reset Control 1 Register MPU Reset Control 2 Register MPU System Status Register ACCESS WIDTH 32 32 32 32 32 32 32 ACCESS TYPE RW RW RW RW RW RW RW RESET VALUE 3000h 0400h 0100h 003Fh 0000h 0000h 0038h Table 3-48. DPLL1 Register BYTE ADDRESS FFFE:CF00 REGISTER NAME DPLL1_CTL_REG DESCRIPTION DPLL1 Control Register ACCESS WIDTH 32 ACCESS TYPE RW RESET VALUE 0000 2002h August 2002 - Revised August 2004 SPRS197D 93 Functional Overview Table 3-49. Ultra Low-Power Device Module Registers BYTE ADDRESS FFFE:0800 FFFE:0804 FFFE:0808 FFFE:080C FFFE:0810 FFFE:0814 FFFE:0818 - FFFE:0820 FFFE:0824 FFFE:0828 - FFFE:082C FFFE:0830 FFFE:0834 FFFE:0838 FFFE:083C FFFE:0840 FFFE:0844 FFFE:0848 FFFE:084C FFFE:0850 LOCK_TIME_REG APLL_CTRL_REG POWER_CTRL_REG CLOCK_CTRL_REG SOFT_REQ_REG COUNTER_32_FIQ_REG DPLL_CTRL_REG STATUS_REQ_REG SETUP_ULPD1_REG REGISTER NAME COUNTER_32_LSB COUNTER_32_MSB COUNTER_HIGH_FREQ_LSB COUNTER_HIGH_FREQ_MSB GAUGING_CTRL_REG IT_STATUS_REG DESCRIPTION ULPD 32-kHz Counter Register LSB ULPD 32-kHz Counter Register MSB ULPD High-Frequency Counter LSB Register ULPD High-Frequency Counter MSB Register ULPD Gauging Control Register ULPD Interrupt Status Register Reserved ULPD Wakeup Time Setup Register Reserved ULPD Clock Control Register ULPD Soft Clock Request Register ULPD Modem Shutdown Delay Register ULPD USB DPLL Control Register ULPD Hardware Request Status Register Reserved ULPD APLL Lock Time Register ULPD APLL Control Register ULPD Power Control Register 16 16 16 RW RW RW 0960h undef 0008h 16 16 16 16 16 RW RW RW RW RW 0000h 0000h 0001h 2211h undef 16 RW 03FFh ACCESS WIDTH 16 16 16 16 16 16 ACCESS TYPE R R R R RW R RESET VALUE 0001h 0001h 0001h 0000h 0000h 0000h Table 3-50. Device Die Identification Registers BYTE ADDRESS FFFE:1800 FFFE:1804 REGISTER NAME DIE_ID_LSB DIE_ID_MSB DESCRIPTION Device Die Identification Register (LSB) Device Die Identification Register (MSB) ACCESS WIDTH 32 32 ACCESS TYPE R R RESET VALUE - - Table 3-51. JTAG Identification Code Register BYTE ADDRESS FFFE:D404 JTAG_ID REGISTER NAME DESCRIPTION JTAG Identification Code Register ACCESS WIDTH 32 ACCESS TYPE R RESET VALUE - 94 SPRS197D August 2002 - Revised August 2004 Functional Overview 3.16 DSP Register Descriptions The following tables describe the DSP registers including register addresses, descriptions, required access widths, access types (R-read, W-write, RW-read/write) and reset values. These tables are organized by function with like peripherals or functions together and are therefore not necessarily in the order of ascending register addresses. NOTE: All accesses to these registers must be of the data access widths indicated to avoid a TIPB bus error condition and a corresponding interrupt. Reserved addresses should never be accessed 3.16.1 * * DSP Private Peripheral Registers DMA Controller: - - - - - DSP DMA Controller Registers DSP Timer 1 Registers DSP Timer 2 Registers DSP Timer 3 Registers DSP Watchdog Timer Registers DSP Interrupt Interface Registers DSP Level 2 Interrupt Handler Registers Timers: The DSP private peripheral registers include the following: * Interrupt Control: - - August 2002 - Revised August 2004 SPRS197D 95 Functional Overview Table 3-52. DSP DMA Controller Registers DSP WORD ADDRESS 0x00 0C00h 0x00 0C01h 0x00 0C02h 0x00 0C03h 0x00 0C04h 0x00 0C05h 0x00 0C06h 0x00 0C07h 0x00 0C08h 0x00 0C09h 0x00 0C0Ah 0x00 0C0Bh 0x00 0C0Ch 0x00 0C0Dh 0x00 0C0Eh 0x00 0C0Fh 0x00 0C10h - 0x00 0C1Fh 0x00 0C20h 0x00 0C21h 0x00 0C22h 0x00 0C23h 0x00 0C24h 0x00 0C25h 0x00 0C26h 0x00 0C27h 0x00 0C28h 0x00 0C29h 0x00 0C2Ah 0x00 0C2Bh 0x00 0C2Ch 0x00 0C2Dh 0x00 0C2Eh 0x00 0C2Fh 0x00 0C30h - 0x00 0C3Fh 0x00 0C40h 0x00 0C41h 0x00 0C42h 0x00 0C43h 0x00 0C44h 0x00 0C45h 0x00 0C46h 0x00 0C47h DMA_CSDP2 DMA_CCR2 DMA_CICR2 DMA_CSR2 DMA_CSSA_L2 DMA_CSSA_U2 DMA_CDSA_L2 DMA_CDSA_U2 DMA_CSDP1 DMA_CCR1 DMA_CICR1 DMA_CSR1 DMA_CSSA_L1 DMA_CSSA_U1 DMA_CDSA_L1 DMA_CDSA_U1 DMA_CEN1 DMA_CFN1 DMA_CSFI1 DMA_CSEI1 DMA_CSAC1 DMA_CDAC1 DMA_CDFI1 DMA_CDEI1 REGISTER NAME DMA_CSDP0 DMA_CCR0 DMA_CICR0 DMA_CSR0 DMA_CSSA_L0 DMA_CSSA_U0 DMA_CDSA_L0 DMA_CDSA_U0 DMA_CEN0 DMA_CFN0 DMA_CSFI0 DMA_CSEI0 DMA_CSAC0 DMA_CDAC0 DMA_CDFI0 DMA_CDEI0 DESCRIPTION Channel 0 Source/Destination Parameters Register Channel 0 Control Register Channel 0 Interrupt Control Register Channel 0 Status Register Channel 0 Source Start Address Register LSB Channel 0 Source Start Address Register MSB Channel 0 Destination Start Address Register LSB Channel 0 Destination Start Address Register MSB Channel 0 Element Number Register Channel 0 Frame Number Register Channel 0 Frame Index Register Channel 0 Element Index Register Channel 0 Source Address Counter Register Channel 0 Destination Address Counter Register Channel 0 Destination Frame Index Channel 0 Destination Element Index Reserved Channel 1 Source/Destination Parameters Register Channel 1 Control Register Channel 1 Interrupt Control Register Channel 1 Status Register Channel 1 Source Start Address Register LSB Channel 1 Source Start Address Register MSB Channel 1 Destination Start Address Register LSB Channel 1 Destination Start Address Register MSB Channel 1 Element Number Register Channel 1 Frame Number Register Channel 1 Frame Index Register Channel 1 Element Index Register Channel 1 Source Address Counter Register Channel 1 Destination Address Counter Register Channel 1 Destination Frame Index Channel 1 Destination Element Index Reserved Channel 2 Source/Destination Parameters Register Channel 2 Control Register Channel 2 Interrupt Control Register Channel 2 Status Register Channel 2 Source Start Address Register LSB Channel 2 Source Start Address Register MSB Channel 2 Destination Start Address Register LSB Channel 2 Destination Start Address Register MSB 16 16 16 16 16 16 16 16 RW RW RW R RW RW RW RW 0000h 0000h 0003h 0000h undef undef undef undef 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 RW RW RW R RW RW RW RW RW RW RW RW RW RW RW RW 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef undef undef undef undef ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE RW RW RW R RW RW RW RW RW RW RW RW RW RW RW RW RESET VALUE 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef undef undef undef undef 96 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-52. DSP DMA Controller Registers (Continued) DSP WORD ADDRESS 0x00 0C48h 0x00 0C49h 0x00 0C4Ah 0x00 0C4Bh 0x00 0C4Ch 0x00 0C4Dh 0x00 0C4Eh 0x00 0C4Fh 0x00 0C50h - 0x00 0C5Fh 0x00 0C60h 0x00 0C61h 0x00 0C62h 0x00 0C63h 0x00 0C64h 0x00 0C65h 0x00 0C66h 0x00 0C67h 0x00 0C68h 0x00 0C69h 0x00 0C6Ah 0x00 0C6Bh 0x00 0C6Ch 0x00 0C6Dh 0x00 0C6Eh 0x00 0C6Fh 0x00 0C70h - 0x00 0C7Fh 0x00 0C80h 0x00 0C81h 0x00 0C82h 0x00 0C83h 0x00 0C84h 0x00 0C85h 0x00 0C86h 0x00 0C87h 0x00 0C88h 0x00 0C89h 0x00 0C8Ah 0x00 0C8Bh 0x00 0C8Ch 0x00 0C8Dh 0x00 0C8Eh 0x00 0C8Fh DMA_CSDP4 DMA_CCR4 DMA_CICR4 DMA_CSR4 DMA_CSSA_L4 DMA_CSSA_U4 DMA_CDSA_L4 DMA_CDSA_U4 DMA_CEN4 DMA_CFN4 DMA_CSFI4 DMA_CSEI4 DMA_CSAC4 DMA_CDAC4 DMA_CDFI4 DMA_CDEI4 DMA_CSDP3 DMA_CCR3 DMA_CICR3 DMA_CSR3 DMA_CSSA_L3 DMA_CSSA_U3 DMA_CDSA_L3 DMA_CDSA_U3 DMA_CEN3 DMA_CFN3 DMA_CSFI3 DMA_CSEI3 DMA_CSAC3 DMA_CDAC3 DMA_CDFI3 DMA_CDEI3 REGISTER NAME DMA_CEN2 DMA_CFN2 DMA_CSFI2 DMA_CSEI2 DMA_CSAC2 DMA_CDAC2 DMA_CDFI2 DMA_CDEI2 DESCRIPTION Channel 2 Element Number Register Channel 2 Frame Number Register Channel 2 Frame Index Register Channel 2 Element Index Register Channel 2 Source Address Counter Register Channel 2 Destination Address Counter Register Channel 2 Destination Frame Index Channel 2 Destination Element Index Reserved Channel 3 Source/Destination Parameters Register Channel 3 Control Register Channel 3 Interrupt Control Register Channel 3 Status Register Channel 3 Source Start Address Register LSB Channel 3 Source Start Address Register MSB Channel 3 Destination Start Address Register LSB Channel 3 Destination Start Address Register MSB Channel 3 Element Number Register Channel 3 Frame Number Register Channel 3 Frame Index Register Channel 3 Element Index Register Channel 3 Source Address Counter Register Channel 3 Destination Address Counter Register Channel 3 Destination Frame Index Channel 3 Destination Element Index Reserved Channel 4 Source/Destination Parameters Register Channel 4 Control Register Channel 4 Interrupt Control Register Channel 4 Status Register Channel 4 Source Start Address Register LSB Channel 4 Source Start Address Register MSB Channel 4 Destination Start Address Register LSB Channel 4 Destination Start Address Register MSB Channel 4 Element Number Register Channel 4 Frame Number Register Channel 4 Frame Index Register Channel 4 Element Index Register Channel 4 Source Address Counter Register Channel 4 Destination Address Counter Register Channel 4 Destination Frame Index Channel 4 Destination Element Index 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 RW RW RW R RW RW RW RW RW RW RW RW RW RW RW RW 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef undef undef undef undef 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 RW RW RW R RW RW RW RW RW RW RW RW RW RW RW RW 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef undef undef undef undef ACCESS WIDTH 16 16 16 16 16 16 16 16 ACCESS TYPE RW RW RW RW RW RW RW RW RESET VALUE undef undef undef undef undef undef undef undef August 2002 - Revised August 2004 SPRS197D 97 Functional Overview Table 3-52. DSP DMA Controller Registers (Continued) DSP WORD ADDRESS 0x00 0C90h - 0x00 0C9Fh 0x00 0CA0h 0x00 0CA1h 0x00 0CA2h 0x00 0CA3h 0x00 0CA4h 0x00 0CA5h 0x00 0CA6h 0x00 0CA7h 0x00 0CA8h 0x00 0CA9h 0x00 0CAAh 0x00 0CABh 0x00 0CACh 0x00 0CADh 0x00 0CAEh 0x00 0CAFh 0x00 0CB0h - 0x00 0DFFh 0x00 0E00h 0x00 0E01h 0x00 0E02h DMA_GCR DMA_GTCR DMA_GSCR DMA_CSDP5 DMA_CCR5 DMA_CICR5 DMA_CSR5 DMA_CSSA_L5 DMA_CSSA_U5 DMA_CDSA_L5 DMA_CDSA_U5 DMA_CEN5 DMA_CFN5 DMA_CSFI5 DMA_CSEI5 DMA_CSAC5 DMA_CDAC5 DMA_CDFI5 DMA_CDEI5 REGISTER NAME Reserved Channel 5 Source/Destination Parameters Register Channel 5 Control Register Channel 5 Interrupt Control Register Channel 5 Status Register Channel 5 Source Start Address Register LSB Channel 5 Source Start Address Register MSB Channel 5 Destination Start Address Register LSB Channel 5 Destination Start Address Register MSB Channel 5 Element Number Register Channel 5 Frame Number Register Channel 5 Frame Index Register Channel 5 Element Index Register Channel 5 Source Address Counter Register Channel 5 Destination Address Counter Register Channel 5 Destination Frame Index Channel 5 Destination Element Index Reserved Global Control Register Global Timeout Control Register Global Software Incompatible Control Register 16 16 16 RW RW RW 0008h 0000h 0000h 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 RW RW RW R RW RW RW RW RW RW RW RW RW RW RW RW 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef undef undef undef undef DESCRIPTION ACCESS WIDTH ACCESS TYPE RESET VALUE 98 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-53. DSP Timer 1 Registers DSP WORD ADDRESS 0x00 2800h 0x00 2801h 0x00 2802h 0x00 2803h 0x00 2804h 0x00 2805h DSP_LOAD_TIM_HI_1 DSP_LOAD_TIM_LO_1 DSP_READ_TIM_HI_1 DSP_READ_TIM_LO_1 REGISTER NAME DSP_CNTL_TIMER_1 DESCRIPTION DSP Timer 1 Control Timer Register Reserved DSP Timer 1 Load Timer High Register DSP Timer 1 Load Timer Low Register DSP Timer 1 Read Timer High Register DSP Timer 1 Read Timer Low Register 16 16 16 16 W W R R undef undef undef undef ACCESS WIDTH 16 ACCESS TYPE RW RESET VALUE 0000h Table 3-54. DSP Timer 2 Registers DSP WORD ADDRESS 0x00 2C00h 0x00 2C01h 0x00 2C02h 0x00 2C03h 0x00 2C04h 0x00 2C05h DSP_LOAD_TIM_HI_2 DSP_LOAD_TIM_LO_2 DSP_READ_TIM_HI_2 DSP_READ_TIM_LO_2 REGISTER NAME DSP_CNTL_TIMER_2 DESCRIPTION DSP Timer 2 Control Timer Register Reserved DSP Timer 2 Load Timer High Register DSP Timer 2 Load Timer Low Register DSP Timer 2 Read Timer High Register DSP Timer 2 Read Timer Low Register 16 16 16 16 W W R R undef undef undef undef ACCESS WIDTH 16 ACCESS TYPE RW RESET VALUE 0000h Table 3-55. DSP Timer 3 Registers DSP WORD ADDRESS 0x00 3000h 0x00 3001h 0x00 3002h 0x00 3003h 0x00 3004h 0x00 3005h DSP_LOAD_TIM_HI_3 DSP_LOAD_TIM_LO_3 DSP_READ_TIM_HI_3 DSP_READ_TIM_LO_3 REGISTER NAME DSP_CNTL_TIMER_3 DESCRIPTION DSP Timer 3 Control Timer Register Reserved DSP Timer 3 Load Timer High Register DSP Timer 3 Load Timer Low Register DSP Timer 3 Read Timer High Register DSP Timer 3 Read Timer Low Register 16 16 16 16 W W R R undef undef undef undef ACCESS WIDTH 16 ACCESS TYPE RW RESET VALUE 0000h Table 3-56. DSP Watchdog Timer Registers DSP WORD ADDRESS 0x00 3400h 0x00 3401h 0x00 3402h 0x00 3402h 0x00 3403h 0x00 3404h DSP_TIMER_MODE_WD DSP_LOAD_TIM_WD DSP_READ_TIM_WD REGISTER NAME DSP_CNTL_TIMER_WD DESCRIPTION DSP WDT Control Timer Register Reserved DSP WDT Load Timer Register DSP WDT Read Timer Register Reserved DSP WDT Timer Mode Register 16 RW 8000h 16 16 W R FFFFh FFFFh ACCESS WIDTH 16 ACCESS TYPE RW RESET VALUE 0002h Table 3-57. DSP Interrupt Interface Registers DSP WORD ADDRESS 0x00 3800h 0x00 3801h 0x00 3802h 0x00 3803h REGISTER NAME ET_LS_CTRL_HI ET_LS_CTRL_LO RST_LVL_LO RST_LVL_HI DESCRIPTION Edge Triggered/Level Sensitive Control Register High Edge Triggered/Level Sensitive Control Register Low Level Sensitive Clear Low Register Level Sensitive Clear High Register ACCESS WIDTH 16 16 16 16 ACCESS TYPE RW RW W W RESET VALUE 0000h 0000h 0000h 0000h August 2002 - Revised August 2004 SPRS197D 99 Functional Overview Table 3-58. DSP Level 2 Interrupt Handler Registers DSP WORD ADDRESS 0x00 4800h 0x00 4802h 0x00 4804h 0x00 4806h 0x00 4808h 0x00 480Ah 0x00 480Ch 0x00 480Eh 0x00 4810h 0x00 4812h 0x00 4814h 0x00 4816h 0x00 4818h 0x00 481Ah 0x00 481Ch 0x00 481Eh 0x00 4820h 0x00 4822h 0x00 4824h 0x00 4826h 0x00 4828h 0x00 482Ah REGISTER NAME DSP_L2_ITR DSP_L2_MIR DSP_L2_SIR_IRQ_CODE DSP_L2_SIR_FIQ_CODE DSP_L2_CONTROL_REG DSP_L2_ISR DSP_L2_ILR0 DSP_L2_ILR1 DSP_L2_ILR2 DSP_L2_ILR3 DSP_L2_ILR4 DSP_L2_ILR5 DSP_L2_ILR6 DSP_L2_ILR7 DSP_L2_ILR8 DSP_L2_ILR9 DSP_L2_ILR10 DSP_L2_ILR11 DSP_L2_ILR12 DSP_L2_ILR13 DSP_L2_ILR14 DSP_L2_ILR15 DESCRIPTION Interrupt Register Mask Interrupt Register IRQ Interrupt Encoded Source Register FIQ Interrupt Encoded Source Register Interrupt Control Register Software Interrupt Set Register Interrupt 0 Priority Level Register Interrupt 1 Priority Level Register Interrupt 2 Priority Level Register Interrupt 3 Priority Level Register Interrupt 4 Priority Level Register Interrupt 5 Priority Level Register Interrupt 6 Priority Level Register Interrupt 7 Priority Level Register Interrupt 8 Priority Level Register Interrupt 9 Priority Level Register Interrupt 10 Priority Level Register Interrupt 11 Priority Level Register Interrupt 12 Priority Level Register Interrupt 13 Priority Level Register Interrupt 14 Priority Level Register Interrupt 15 Priority Level Register ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE RW RW R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RESET VALUE 0000h FFFFh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 100 SPRS197D August 2002 - Revised August 2004 Functional Overview 3.16.2 * DSP Public Peripheral Registers Serial Ports: - - - - McBSP1 Registers McBSP3 Registers MCSI1 Registers MCSI2 Registers Table 3-59. McBSP1 Registers MPU BYTE ADDRESS (VIA MPUI) E101:1800 E101:1802 E101:1804 E101:1806 E101:1808 E101:180A E101:180C E101:180E E101:1810 E101:1812 E101:1814 E101:1816 E101:1818 E101:181A E101:181C E101:181E E101:1820 E101:1822 E101:1824 E101:1826 E101:1828 E101:182A E101:182C E101:182E E101:1830 E101:1832 E101:1834 The DSP public peripheral registers include the following: DSP WORD ADDRESS 0x00 8C00h 0x00 8C01h 0x00 8C02h 0x00 8C03h 0x00 8C04h 0x00 8C05h 0x00 8C06h 0x00 8C07h 0x00 8C08h 0x00 8C09h 0x00 8C0Ah 0x00 8C0Bh 0x00 8C0Ch 0x00 8C0Dh 0x00 8C0Eh 0x00 8C0Fh 0x00 8C10h 0x00 8C11h 0x00 8C12h 0x00 8C13h 0x00 8C14h 0x00 8C15h 0x00 8C16h 0x00 8C17h 0x00 8C18h 0x00 8C19h 0x00 8C1Ah REGISTER NAME MCBSP1_DRR2 MCBSP1_DRR1 MCBSP1_DXR2 MCBSP1_DXR1 MCBSP1_SPCR2 MCBSP1_SPCR1 MCBSP1_RCR2 MCBSP1_RCR1 MCBSP1_XCR2 MCBSP1_XCR1 MCBSP1_SRGR2 MCBSP1_SRGR1 MCBSP1_MCR2 MCBSP1_MCR1 MCBSP1_RCERA MCBSP1_RCERB MCBSP1_XCERA MCBSP1_XCERB MCBSP1_PCR0 MCBSP1_RCERC MCBSP1_RCERD MCBSP1_XCERC MCBSP1_XCERD MCBSP1_RCERE MCBSP1_RCERF MCBSP1_XCERE MCBSP1_XCERF DESCRIPTION McBSP1 Data Receive Register 2 McBSP1 Data Receive Register 1 McBSP1 Data Transmit Register 2 McBSP1 Data Transmit Register 1 McBSP1 Serial Port Control Register 2 McBSP1 Serial Port Control Register 1 McBSP1 Receive Control Register 2 McBSP1 Receive Control Register 1 McBSP1 Transmit Control Register 2 McBSP1 Transmit Control Register 1 McBSP1 Sample Rate Generator Register 2 McBSP1 Sample Rate Generator Register 1 McBSP1 Multichannel Control Register 2 McBSP1 Multichannel Control Register 1 McBSP1 Receive Channel Enable Register Partition A McBSP1 Receive Channel Enable Register Partition B McBSP1 Transmit Channel Enable Register Partition A McBSP1 Transmit Channel Enable Register Partition B McBSP1 Pin Control Register 0 McBSP1 Receive Channel Enable Register Partition C McBSP1 Receive Channel Enable Register Partition D McBSP1 Transmit Channel Enable Register Partition C McBSP1 Transmit Channel Enable Register Partition D McBSP1 Receive Channel Enable Register Partition E McBSP1 Receive Channel Enable Register Partition F McBSP1 Transmit Channel Enable Register Partition E McBSP1 Transmit Channel Enable Register Partition F ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 2000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h August 2002 - Revised August 2004 SPRS197D 101 Functional Overview Table 3-59. McBSP1 Registers (Continued) DSP WORD ADDRESS 0x00 8C1Bh 0x00 8C1Ch 0x00 8C1Dh 0x00 8C1Eh MPU BYTE ADDRESS (VIA MPUI) E101:1836 E101:1838 E101:183A E101:183C REGISTER NAME MCBSP1_RCERG MCBSP1_RCERH MCBSP1_XCERG MCBSP1_XCERH DESCRIPTION McBSP1 Receive Channel Enable Register Partition G McBSP1 Receive Channel Enable Register Partition H McBSP1 Transmit Channel Enable Register Partition G McBSP1 Transmit Channel Enable Register Partition H ACCESS WIDTH 16 16 16 16 ACCESS TYPE RW RW RW RW RESET VALUE 0000h 0000h 0000h 0000h Table 3-60. McBSP3 Registers MPU BYTE DSP WORD ADDRESS ADDRESS (VIA MPUI) 0x00 B800h 0x00 B801h 0x00 B802h 0x00 B803h 0x00 B804h 0x00 B805h 0x00 B806h 0x00 B807h 0x00 B808h 0x00 B809h 0x00 B80Ah 0x00 B80Bh E101:7000 E101:7002 E101:7004 E101:7006 E101:7008 E101:700A E101:700C E101:700E E101:7010 E101:7012 E101:7014 E101:7016 REGISTER NAME MCBSP3_DRR2 MCBSP3_DRR1 MCBSP3_DXR2 MCBSP3_DXR1 MCBSP3_SPCR2 MCBSP3_SPCR1 MCBSP3_RCR2 MCBSP3_RCR1 MCBSP3_XCR2 MCBSP3_XCR1 MCBSP3_SRGR2 MCBSP3_SRGR1 MCBSP3_MCR2 MCBSP3_MCR1 MCBSP3_RCERA MCBSP3_RCERB MCBSP3_XCERA MCBSP3_XCERB MCBSP3_PCR0 MCBSP3_RCERC MCBSP3_RCERD MCBSP3_XCERC MCBSP3_XCERD MCBSP3_RCERE MCBSP3_RCERF DESCRIPTION McBSP3 Data Receive Register 2 McBSP3 Data Receive Register 1 McBSP3 Data Transmit Register 2 McBSP3 Data Transmit Register 1 McBSP3 Serial Port Control Register 2 McBSP3 Serial Port Control Register 1 McBSP3 Receive Control Register 2 McBSP3 Receive Control Register 1 McBSP3 Transmit Control Register 2 McBSP3 Transmit Control Register 1 McBSP3 Sample Rate Generator Register 2 McBSP3 Sample Rate Generator Register 1 McBSP3 Multichannel Control Register 2 McBSP3 Multichannel Control Register 1 McBSP3 Receive Channel Enable Register Partition A McBSP3 Receive Channel Enable Register Partition B McBSP3 Transmit Channel Enable Register Partition A McBSP3 Transmit Channel Enable Register Partition B McBSP3 Pin Control Register 0 McBSP3 Receive Channel Enable Register Partition C McBSP3 Receive Channel Enable Register Partition D McBSP3 Transmit Channel Enable Register Partition C McBSP3 Transmit Channel Enable Register Partition D McBSP3 Receive Channel Enable Register Partition E McBSP3 Receive Channel Enable Register Partition F ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 2000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0x00 B80Ch E101:7018 0x00 B80Dh E101:701A 0x00 B80Eh 0x00 B80Fh 0x00 B810h 0x00 B811h 0x00 B812h 0x00 B813h 0x00 B814h 0x00 B815h 0x00 B816h 0x00 B817h 0x00 B818h E101:701C E101:701E E101:7020 E101:7022 E101:7024 E101:7026 E101:7028 E101:702A E101:702C E101:702E E101:7030 102 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-60. McBSP3 Registers (Continued) MPU BYTE DSP WORD ADDRESS ADDRESS (VIA MPUI) 0x00 B819h 0x00 B81Ah 0x00 B81Bh E101:7032 E101:7034 E101:7036 REGISTER NAME MCBSP3_XCERE MCBSP3_XCERF MCBSP3_RCERG MCBSP3_RCERH MCBSP3_XCERG MCBSP3_XCERH DESCRIPTION McBSP3 Transmit Channel Enable Register Partition E McBSP3 Transmit Channel Enable Register Partition F McBSP3 Receive Channel Enable Register Partition G McBSP3 Receive Channel Enable Register Partition H McBSP3 Transmit Channel Enable Register Partition G McBSP3 Transmit Channel Enable Register Partition H ACCESS WIDTH 16 16 16 16 16 16 ACCESS TYPE RW RW RW RW RW RW RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0x00 B81Ch E101:7038 0x00 B81Dh E101:703A 0x00 B81Eh E101:703C August 2002 - Revised August 2004 SPRS197D 103 Functional Overview Table 3-61. MCSI1 Registers DSP WORD ADDRESS 0x00 9400h 0x00 9401h 0x00 9402h 0x00 9403h 0x00 9404h 0x00 9405h 0x00 9406h 0x00 9407h- 0x00 941Fh 0x00 9420h 0x00 9421h 0x00 9422h 0x00 9423h 0x00 9424h 0x00 9425h 0x00 9426h 0x00 9427h 0x00 9428h 0x00 9429h 0x00 942Ah 0x00 942Bh 0x00 942Ch 0x00 942Dh 0x00 942Eh 0x00 942Fh 0x00 9430h 0x00 9431h 0x00 9432h 0x00 9433h 0x00 9434h 0x00 9435h 0x00 9436h 0x00 9437h 0x00 9438h 0x00 9439h 0x00 943Ah 0x00 943Bh 0x00 943Ch 0x00 943Dh 0x00 943Eh 0x00 943Fh E101:2840 E101:2842 E101:2844 E101:2846 E101:2848 E101:284A E101:284C E101:284E E101:2850 E101:2852 E101:2854 E101:2856 E101:2858 E101:285A E101:285C E101:285E E101:2860 E101:2862 E101:2864 E101:2866 E101:2868 E101:286A E101:286C E101:286E E101:2870 E101:2872 E101:2874 E101:2876 E101:2878 E101:287A E101:287C E101:287E MPU BYTE ADDRESS (VIA MPUI) E101:2800 E101:2802 E101:2804 E101:2806 E101:2808 E101:280A E101:280C REGISTER NAME MCSI1_CONTROL_REG MCSI1_MAIN_PARAMETERS_REG MCSI1_INTERRUPTS_REG MCSI1_CHANNEL_USED_REG MCSI1_OVER_CLOCK_REG MCSI1_CLOCK_FREQUENCY_ REG MCSI1_STATUS_REG Reserved MCSI1_TX0 MCSI1_TX1 MCSI1_TX2 MCSI1_TX3 MCSI1_TX4 MCSI1_TX5 MCSI1_TX6 MCSI1_TX7 MCSI1_TX8 MCSI1_TX9 MCSI1_TX10 MCSI1_TX11 MCSI1_TX12 MCSI1_TX13 MCSI1_TX14 MCSI1_TX15 MCSI1_RX0 MCSI1_RX1 MCSI1_RX2 MCSI1_RX3 MCSI1_RX4 MCSI1_RX5 MCSI1_RX6 MCSI1_RX7 MCSI1_RX8 MCSI1_RX9 MCSI1_RX10 MCSI1_RX11 MCSI1_RX12 MCSI1_RX13 MCSI1_RX14 MCSI1_RX15 MCSI1 Transmit Word Register 0 MCSI1 Transmit Word Register 1 MCSI1 Transmit Word Register 2 MCSI1 Transmit Word Register 3 MCSI1 Transmit Word Register 4 MCSI1 Transmit Word Register 5 MCSI1 Transmit Word Register 6 MCSI1 Transmit Word Register 7 MCSI1 Transmit Word Register 8 MCSI1 Transmit Word Register 9 MCSI1 Transmit Word Register 10 MCSI1 Transmit Word Register 11 MCSI1 Transmit Word Register 12 MCSI1 Transmit Word Register 13 MCSI1 Transmit Word Register 14 MCSI1 Transmit Word Register 15 MCSI1 Receive Word Register 0 MCSI1 Receive Word Register 1 MCSI1 Receive Word Register 2 MCSI1 Receive Word Register 3 MCSI1 Receive Word Register 4 MCSI1 Receive Word Register 5 MCSI1 Receive Word Register 6 MCSI1 Receive Word Register 7 MCSI1 Receive Word Register 8 MCSI1 Receive Word Register 9 MCSI1 Receive Word Register 10 MCSI1 Receive Word Register 11 MCSI1 Receive Word Register 12 MCSI1 Receive Word Register 13 MCSI1 Receive Word Register 14 MCSI1 Receive Word Register 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R R R R R R R R R R R R R R R Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined DESCRIPTION MCSI1 Control Register MCSI1 Main Parameters Register MCSI1 Interrupts Register MCSI1 Channel Used Register MCSI1 Over-Clock Register MCSI1 Clock Frequency Register MCSI1 Status Register ACCESS ACCESS WIDTH TYPE 16 16 16 16 16 16 16 RW RW RW RW RW RW RW RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h 104 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-62. MCSI2 Registers DSP WORD ADDRESS 0x00 9000h 0x00 9001h 0x00 9002h 0x00 9003h 0x00 9004h 0x00 9005h 0x00 9006h 0x00 9007h - 0x00 901Fh 0x00 9020h 0x00 9021h 0x00 9022h 0x00 9023h 0x00 9024h 0x00 9025h 0x00 9026h 0x00 9027h 0x00 9028h 0x00 9029h 0x00 902Ah 0x00 902Bh 0x00 902Ch 0x00 902Dh 0x00 902Eh 0x00 902Fh 0x00 9030h 0x00 9031h 0x00 9032h 0x00 9033h 0x00 9034h 0x00 9035h 0x00 9036h 0x00 9037h 0x00 9038h 0x00 9039h 0x00 903Ah 0x00 903Bh 0x00 903Ch 0x00 903Dh 0x00 903Eh 0x00 903Fh E101:2040 E101:2042 E101:2044 E101:2046 E101:2048 E101:204A E101:204C E101:204E E101:2050 E101:2052 E101:2054 E101:2056 E101:2058 E101:205A E101:205C E101:205E E101:2060 E101:2062 E101:2064 E101:2066 E101:2068 E101:206A E101:206C E101:206E E101:2070 E101:2072 E101:2074 E101:2076 E101:2078 E101:207A E101:207C E101:207E MPU BYTE ADDRESS (VIA MPUI) E101:2000 E101:2002 E101:2004 E101:2006 E101:2008 E101:200A E101:200C REGISTER NAME MCSI2_CONTROL_REG MCSI2_MAIN_PARAMETERS_REG MCSI2_INTERRUPTS_REG MCSI2_CHANNEL_USED_REG MCSI2_OVER_CLOCK_REG MCSI2_CLOCK_FREQUENCY_ REG MCSI2_STATUS_REG Reserved MCSI2_TX0 MCSI2_TX1 MCSI2_TX2 MCSI2_TX3 MCSI2_TX4 MCSI2_TX5 MCSI2_TX6 MCSI2_TX7 MCSI2_TX8 MCSI2_TX9 MCSI2_TX10 MCSI2_TX11 MCSI2_TX12 MCSI2_TX13 MCSI2_TX14 MCSI2_TX15 MCSI2_RX0 MCSI2_RX1 MCSI2_RX2 MCSI2_RX3 MCSI2_RX4 MCSI2_RX5 MCSI2_RX6 MCSI2_RX7 MCSI2_RX8 MCSI2_RX9 MCSI2_RX10 MCSI2_RX11 MCSI2_RX12 MCSI2_RX13 MCSI2_RX14 MCSI2_RX15 MCSI2 Transmit Word Register 0 MCSI2 Transmit Word Register 1 MCSI2 Transmit Word Register 2 MCSI2 Transmit Word Register 3 MCSI2 Transmit Word Register 4 MCSI2 Transmit Word Register 5 MCSI2 Transmit Word Register 6 MCSI2 Transmit Word Register 7 MCSI2 Transmit Word Register 8 MCSI2 Transmit Word Register 9 MCSI2 Transmit Word Register 10 MCSI2 Transmit Word Register 11 MCSI2 Transmit Word Register 12 MCSI2 Transmit Word Register 13 MCSI2 Transmit Word Register 14 MCSI2 Transmit Word Register 15 MCSI2 Receive Word Register 0 MCSI2 Receive Word Register 1 MCSI2 Receive Word Register 2 MCSI2 Receive Word Register 3 MCSI2 Receive Word Register 4 MCSI2 Receive Word Register 5 MCSI2 Receive Word Register 6 MCSI2 Receive Word Register 7 MCSI2 Receive Word Register 8 MCSI2 Receive Word Register 9 MCSI2 Receive Word Register 10 MCSI2 Receive Word Register 11 MCSI2 Receive Word Register 12 MCSI2 Receive Word Register 13 MCSI2 Receive Word Register 14 MCSI2 Receive Word Register 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R R R R R R R R R R R R R R R Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined DESCRIPTION MCSI2 control register MCSI2 main parameters register MCSI2 interrupts register MCSI2 channel used register MCSI2 over-clock register MCSI2 clock frequency register MCSI2 status register ACCESS WIDTH 16 16 16 16 16 16 16 ACCESS TYPE RW RW RW RW RW RW RW RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h August 2002 - Revised August 2004 SPRS197D 105 Functional Overview 3.16.3 * DSP Configuration Registers I-Cache and EMIF setup - - DSP Instruction Cache Registers DSP EMIF Configuration Registers DSP TIPB Bridge Configuration Registers DSP UART TI Peripheral Bus Switch Registers DSP Clock Mode Registers Table 3-63. DSP Instruction Cache Registers The DSP configuration registers include the following: * TIPB setup - - * Clock Control: - DSP WORD ADDRESS 0x00 1400h 0x00 1401h 0x00 1402h 0x00 1403h 0x00 1404h 0x00 1405h 0x00 1406h 0x00 1407h 0x00 1408h REGISTER NAME ICGC DESCRIPTION I-Cache Global Control Register Reserved Reserved ACCESS WIDTH 16 16 16 16 16 16 16 16 16 ACCESS TYPE RW RW RW RW R RW RW RW RW RESET VALUE C006h 0000h 0000h 000Dh 0000h 000Dh 0000h 000Dh 0000h ICWC ICST ICRC1 ICRTAG1 ICRC2 ICRTAG2 I-Cache Way Control Register I-Cache Status Register I-Cache Ramset 1 Control Register I-Cache Remset 1 TAG Register I-Cache Ramset 2 Control Register I-Cache Remset 2 TAG Register Table 3-64. DSP EMIF Configuration Register DSP WORD ADDRESS 0x00 0800h 0x00 0801h REGISTER NAME DSP_EMIF_GCR DSP_EMIF_GRR DESCRIPTION DSP EMIF Global Control Register DSP EMIF Global Reset Register ACCESS WIDTH 16 16 ACCESS TYPE RW RW RESET VALUE 0020h undef Table 3-65. DSP TIPB Bridge Configuration Registers DSP WORD ADDRESS 0x00 0000h 0x00 0001h 0x00 0002h REGISTER NAME TIPB_CMR TIPB_ICR TIPB_ISTR DESCRIPTION DSP TIPB Bridge Control Mode Register DSP TIPB Bridge Idle Control Register DSP TIPB Bridge Idle Status Register ACCESS WIDTH 16 16 16 ACCESS TYPE RW RW R RESET VALUE FE4Dh 0000h 0000h 106 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-66. DSP UART TIPB Bus Switch Registers DSP WORD ADDRESS 0x00 E400h 0x00 E402h 0x00 E404- 0x00 E0Eh 0x00 E410h 0x00 E412h 0x00 E414- 0x00 E1Eh 0x00 E420h 0x00 E422h RHSW_DSP_CNF3 RHSW_DSP_STA3 RHSW_DSP_CNF2 RHSW_DSP_STA2 REGISTER NAME RHSW_DSP_CNF1 RHSW_DSP_STA1 DESCRIPTION UART1 TIPB Switch Configuration Register (DSP) UART1 TIPB Switch Status Register (DSP) Reserved UART2 TIPB Switch Configuration Register (DSP) UART2 TIPB Switch Status Register (DSP) Reserved UART3 TIPB Switch Configuration Register (DSP) UART3 TIPB Switch Status Register (DSP) 16 16 RW R 0001h 0001h 16 16 RW R 0001h 0001h ACCESS WIDTH 16 16 ACCESS TYPE RW R RESET VALUE 0001h 0001h Table 3-67. DSP Clock Mode Registers DSP WORD ADDRESS 0x00 4000h 0x00 4002h 0x00 4004h 0x00 4006h - 0x00 4008h 0x00 400Ah 0x00 400Ch E100:8014 E100:8018 MPU BYTE ADDRESS (VIA MPUI) E100:8000 E100:8004 E100:8008 REGISTER NAME DSP_CKCTL DSP_IDLECT1 DSP_IDLECT2 Reserved DSP_RSTCT2 DSP_SYSST DSP Peripheral Reset Control Register DSP System Status Register 16 16 RW RW 0000h 0000h DESCRIPTION DSP Clock Control Register DSP Idle Control 1 Register DSP Idle Control 2 Register ACCESS WIDTH 16 16 16 ACCESS TYPE RW RW RW RESET VALUE 0000h 0000h 0000h August 2002 - Revised August 2004 SPRS197D 107 Functional Overview 3.16.4 MPU/DSP Shared Peripheral Register Descriptions The following tables describe the MPU/DSP shared peripheral registers including register addresses, descriptions, required access widths, access types (R-read, W-write, RW-read/write) and reset values. These tables are organized by function with like peripherals or functions together and are therefore not necessarily in order of ascending register addresses. Reserved addresses should never be accessed. NOTE: All accesses to these registers must be of the data access widths indicated to avoid a TIPB bus error condition and a corresponding interrupt. Reserved addresses should never be accessed. The MPU/DSP shared peripheral registers include the following: * UARTs: - - - * - - UART1 Registers UART2 Registers UART3/IrDA Registers MPU/DSP Shared GPIO Registers MPU/DSP Shared Mailbox Registers GPIO and Mailboxes 108 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-68. UART1 Registers DSP WORD ADDRESS 0x00 8000h 0x00 8000h 0x00 8000h 0x00 8001h 0x00 8001h 0x00 8002h 0x00 8002h 0x00 8002h 0x00 8003h 0x00 8004h 0x00 8004h 0x00 8005h 0x00 8005h 0x00 8006h 0x00 8006h 0x00 8006h 0x00 8007h 0x00 8007h 0x00 8007h 0x00 8008h 0x00 8009h - 0x00 800Dh 0x00 800Eh 0x00 800Fh 0x00 8010h 0x00 8011h 0x00 8012h 0x00 8013h 0x00 8014h MPU BYTE ADDRESS FFFB:0000 FFFB:0000 FFFB:0000 FFFB:0004 FFFB:0004 FFFB:0008 FFFB:0008 FFFB:0008 FFFB:000C FFFB:0010 FFFB:0010 FFFB:0014 FFFB:0014 FFFB:0018 FFFB:0018 FFFB:0018 FFFB:001C FFFB:001C FFFB:001C FFFB:0020 FFFB:0024 - FFFB:0034 FFFB:0038 FFFB:003C FFFB:0040 FFFB:0044 FFFB:0048 FFFB:004C FFFB:0050 MPU BYTE ADDRESS (VIA MPUI) E101:0000 E101:0000 E101:0000 E101:0002 E101:0002 E101:0004 E101:0004 E101:0004 E101:0006 E101:0008 E101:0008 E101:000A E101:000A E101:000C E101:000C E101:000C E101:000E E101:000E E101:000E E101:0010 REGISTER NAME UART1_RHR UART1_THR UART1_DLL UART1_IER UART1_DLH UART1_IIR UART1_FCR UART1_EFR UART1_LCR UART1_MCR UART1_XON1 UART1_LSR UART1_XON2 UART1_MSR UART1_TCR# UART1_XOFF1 UART1_SPR UART1_TLR# UART1_XOFF2 UART1_MDR1 DESCRIPTION UART1 Receive Holding Register UART1 Transmit Holding Register UART1 Divisor Latch Low Register UART1 Interrupt Enable Register UART1 Divisor Latch High Register UART1 Interrupt Identification Register UART1 FIFO Control Register UART1 Enhanced Feature Register UART1 Line Control Register UART1 Modem Control Register UART1 XON1 Register UART1 Mode Register UART1 XON2 Register UART1 Modem Status Register UART1 Transmission Control Register UART1 XOFF1 Register UART1 Scratchpad Register UART1 Trigger Level Register UART1 XOFF2 Register UART1 Mode Definition 1 Register Reserved ACCESS WIDTH 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 ACCESS TYPE R W RW RW RW R W RW RW RW RW R RW R RW RW RW RW RW RW RESET VALUE Undefined Undefined 00h 00h 00h 01h 00h 00h 00h 00h 00h 60h 00h Undefined 0Fh 00h 00h 00h 00h 07h E101:001C UART1_UASR UART1 Autobauding Status Register Reserved UART1 Supplementary Control Register UART1 Supplementary Status Register Reserved UART1 12-/13-MHz Oscillator Select Register UART1 Module Version Register 8 R 00h E101:0020 E101:0022 UART1_SCR UART1_SSR 8 8 RW R 00h 00h E101:0026 E101:0028 UART1_OSC_ 12M_SEL UART1_MVR 8 8 W R 00h - Register is accessible when LCR[7] = 0 (normal operating mode) Register is accessible when LCR[7] = 1 and LCR[7:0] 0BFh Register is accessible when LCR[7] = 0BFh Register is write accessible when EFR[4] = 1 # Register is accessible when EFR[4] = 1 and MCR[6] = 1 August 2002 - Revised August 2004 SPRS197D 109 Functional Overview Table 3-69. UART2 Registers DSP WORD ADDRESS 0x00 8400h 0x00 8400h 0x00 8400h 0x00 8401h 0x00 8401h 0x00 8402h 0x00 8402h 0x00 8402h 0x00 8403h 0x00 8404h 0x00 8404h 0x00 8405h 0x00 8405h 0x00 8406h 0x00 8406h 0x00 8406h 0x00 8407h 0x00 8407h 0x00 8407h 0x00 8408h 0x00 8409 - 0x00840Dh 0x00 840Eh 0x00 840Fh 0x00 8410h 0x00 8411h 0x00 8412h 0x00 8413h 0x00 8414h MPU BYTE ADDRESS FFFB:0800 FFFB:0800 FFFB:0800 FFFB:0804 FFFB:0804 FFFB:0808 FFFB:0808 FFFB:0808 FFFB:080C FFFB:0810 FFFB:0810 FFFB:0814 FFFB:0814 FFFB:0818 FFFB:0818 FFFB:0818 FFFB:081C FFFB:081C FFFB:081C FFFB:0820 FFFB:0824 - FFFB:0834 FFFB:0838 FFFB:083C FFFB:0840 FFFB:0844 FFFB:0848 FFFB:084C FFFB:0850 MPU BYTE ADDRESS (VIA MPUI) E101:0800 E101:0800 E101:0800 E101:0802 E101:0802 E101:0804 E101:0804 E101:0804 E101:0806 E101:0808 E101:0808 E101:080A E101:080A E101:080C E101:080C E101:080C E101:080E E101:080E E101:080E E101:0810 REGISTER NAME UART2_RHR UART2_THR UART2_DLL UART2_IER UART2_DLH UART2_IIR UART2_FCR UART2_EFR UART2_LCR UART2_MCR UART2_XON1 UART2_LSR UART2_XON2 UART2_MSR UART2_TCR# UART2_XOFF1 UART2_SPR UART2_TLR# UART2_XOFF2 UART2_MDR1 DESCRIPTION UART2 Receive Holding Register UART2 Transmit Holding Register UART2 Divisor Latch Low Register UART2 Interrupt Enable Register UART2 Divisor Latch High Register UART2 Interrupt Identification Register UART2 FIFO Control Register UART2 Enhanced Feature Register UART2 Line Control Register UART2 Modem Control Register UART2 XON1 Register UART2 Mode Register UART2 XON2 Register UART2 Modem Status Register UART2 Transmission Control Register UART2 XOFF1 Register UART2 Scratchpad Register UART2 Trigger Level Register UART2 XOFF2 Register UART2 Mode Definition 1 Register Reserved ACCESS WIDTH 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 ACCESS TYPE R W RW RW RW R W RW RW RW RW R RW R RW RW RW RW RW RW RESET VALUE Undefined Undefined 00h 00h 00h 01h 00h 00h 00h 00h 00h 60h 00h Undefined 0Fh 00h 00h 00h 00h 07h E101:081C UART2_UASR UART2 Autobauding Status Register Reserved UART2 Supplementary Control Register UART2 Supplementary Status Register Reserved UART2 12-/13-MHz Oscillator Select Register UART2 Module Version Register 8 R 00h E101:0820 E101:0822 UART2_SCR UART2_SSR 8 8 RW R 00h 00h E101:0826 E101:0828 UART2_OSC_ 12M_SELV UART2_MVR 8 8 W R 00h - Register is accessible when LCR[7] = 0 (normal operating mode) Register is accessible when LCR[7] = 1 and LCR[7:0] 0BFh Register is accessible when LCR[7] = 0BFh Register is write accessible when EFR[4] = 1 # Register is accessible when EFR[4] = 1 and MCR[6] = 1 110 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-70. UART3/IrDA Registers DSP WORD ADDRESS 0x00 CC00h 0x00 CC00h 0x00 CC00h 0x00 CC01h 0x00 CC01h 0x00 CC02h 0x00 CC02h 0x00 CC02h 0x00 CC03h 0x00 CC04h 0x00 CC04h 0x00 CC05h 0x00 CC05h 0x00 CC06h 0x00 CC06h 0x00 CC06h 0x00 CC07h 0x00 CC07h 0x00 CC07h 0x00 CC08h 0x00 CC09h 0x00 CC0Ah 0x00 CC0Ah 0x00 CC0Bh 0x00 CC0Bh 0x00 CC0Ch 0x00 CC0Ch 0x00 CC0Dh 0x00 CC0Dh 0x00 CC0Eh 0x00 CC0Fh MPU BYTE ADDRESS FFFB:9800 FFFB:9800 FFFB:9800 FFFB:9804 FFFB:9804 FFFB:9808 FFFB:9808 FFFB:9808 FFFB:980C FFFB:9810 FFFB:9810 FFFB:9814 FFFB:9814 FFFB:9818 FFFB:9818 FFFB:9818 FFFB:981C FFFB:981C FFFB:981C FFFB:9820 FFFB:9824 FFFB:9828 FFFB:9828 FFFB:982C FFFB:982C FFFB:9830 FFFB:9830 FFFB:9834 FFFB:9834 FFFB:9838 FFFB:983C MPU BYTE ADDRESS (VIA MPUI) E101:9800 E101:9800 E101:9800 E101:9802 E101:9802 E101:9804 E101:9804 E101:9804 E101:9806 E101:9808 E101:9808 E101:980A E101:980A E101:980C E101:980C E101:980C E101:980E E101:980E E101:980E E101:9810 E101:9812 E101:9814 E101:9814 E101:9816 E101:9816 E101:9818 E101:9818 E101:981A E101:981A E101:981C E101:981E REGISTER NAME UART3_RHR UART3_THR UART3_DLL UART3_IER UART3_DLH UART3_IIR UART3_FCR UART3_EFR UART3_LCR UART3_MCR UART3_XON1 UART3_LSR UART3_XON2 UART3_MSR UART3_TCR# UART3_XOFF1 UART3_SPR UART3_TLR# UART3_XOFF2 UART3_MDR1 UART3_MDR2 UART3_SFLSR UART3_TXFLL UART3_RESUME UART3_TXFLH UART3_SFREGL UART3_RXFLL UART3_SFREGH UART3_RXFLH UART3_BLR UART3_ACREG DESCRIPTION UART3 Receive Holding Register UART3 Transmit Holding Register UART3 Divisor Latch Low Register UART3 Interrupt Enable Register UART3 Divisor Latch High Register UART3 Interrupt Identification Register UART3 FIFO Control Register UART3 Enhanced Feature Register UART3 Line Control Register UART3 Modem Control Register UART3 XON1 Register UART3 Mode Register UART3 XON2 Register UART3 Modem Status Register UART3 Transmission Control Register UART3 XOFF1 Register UART3 Scratchpad Register UART3 Trigger Level Register UART3 XOFF2 Register UART3 Mode Definition 1 Register UART3 Mode Definition Register 2 UART3 Status FIFO Line Status Register UART3 Transmit Frame Length Low UART3 Resume Register UART3 Transmit Frame Length High UART3 Status FIFO Low Register UART3 Receive Frame Length Low UART3 Status FIFO High Register UART3 Receive Frame Length High UART3 BOF Control Register UART3 Auxiliary Control Register ACCESS WIDTH 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 ACCESS TYPE R W RW RW RW R W RW RW RW RW R RW R RW RW RW RW RW RW RW R W R W R W R W RW RW RESET VALUE Undefined Undefined 00h 00h 00h 01h 00h 00h 00h 00h 00h 60h 00h Undefined 0Fh 00h 00h 00h 00h 07h 00h 00h 00h 00h 00h Undefined 00h Undefined 00h 40h 00h Register is accessible when LCR[7] = 0 (normal operating mode) Register is accessible when LCR[7] = 1 and LCR[7:0] 0BFh Register is accessible when LCR[7] = 0BFh Register is write accessible when EFR[4] = 1 # Register is accessible when EFR[4] = 1 and MCR[6] = 1 August 2002 - Revised August 2004 SPRS197D 111 Functional Overview Table 3-70. UART3/IrDA Registers (Continued) DSP WORD ADDRESS 0x00 CC0Fh 0x00 CC10h MPU BYTE ADDRESS FFFB:983C FFFB:9840 MPU BYTE ADDRESS (VIA MPUI) E101:981E E101:9820 REGISTER NAME UART3_DIV16 UART3_SCR DESCRIPTION UART3 Divide 1.6 Register UART3 Supplementary Control Register ACCESS ACCESS WIDTH TYPE 8 8 RW RW RESET VALUE 00h 00h Register is accessible when LCR[7] = 0 (normal operating mode) Register is accessible when LCR[7] = 1 and LCR[7:0] 0BFh Register is accessible when LCR[7] = 0BFh Register is write accessible when EFR[4] = 1 # Register is accessible when EFR[4] = 1 and MCR[6] = 1 Table 3-71. MPU/DSP Shared GPIO Registers DSP WORD ADDRESS 0x00 F000h 0x00 F002h 0x00 F004h 0x00 F006h 0x00 F008h 0x00 F00Ah 0x00 F00Ch MPU BYTE ADDRESS FFFC:E000 FFFC:E004 FFFC:E008 FFFC:E00C FFFC:E010 FFFC:E014 FFFC:E018 REGISTER NAME DATA_INPUT DATA_OUTPUT DIRECTION_CONTROL INTERRUPT_CONTROL INTERRUPT_MASK INTERRUPT_STATUS PIN_CONTROL DESCRIPTION Data Input Register Data Output Register Direction Control Register Interrupt Control Register Interrupt Mask Register Interrupt Status Register Pin Control Register ACCESS WIDTH 16 16 16 16 16 16 16 MPU ACCESS R RW RW RW RW RW RW DSP ACCESS R RW RW RW RW RW R RESET VALUE 0000h FFFFh FFFFh FFFFh FFFFh 0000h FFFFh Table 3-72. MPU/DSP Shared Mailbox Registers DSP WORD ADDRESS 0x00 F800h 0x00 F802h 0x00 F804h 0x00 F806h 0x00 F808h 0x00 F80Ah 0x00 F80Ch 0x00 F80Eh 0x00 F810h 0x00 F812h 0x00 F814h 0x00 F816h MPU BYTE ADDRESS FFFC:F000 FFFC:F004 FFFC:F008 FFFC:F00C FFFC:F010 FFFC:F014 FFFC:F018 FFFC:F01C FFFC:F020 FFFC:F024 FFFC:F028 FFFC:F02C REGISTER NAME ARM2DSP1 ARM2DSP1B DSP2ARM1 DSP2ARM1B DSP2ARM2 DSP2ARM2B ARM2DSP1_FLAG DSP2ARM1_FLAG DSP2ARM2_FLAG ARM2DSP2 ARM2DSP2B ARM2DSP2_FLAG DESCRIPTION MPU to DSP 1 Data Register MPU to DSP 1 Command Register DSP to MPU 1 Data Register DSP to MPU 1 Command Register DSP to MPU 2 Data Register DSP to MPU 2 Command Register MPU to DSP 1 Flag Register DSP to MPU 1 Flag Register DSP to MPU 2 Flag Register MPU to DSP 2 Data Register MPU to DSP 2 Command Register MPU to DSP 2 Flag Register ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 MPU ACCESS TYPE RW RW R R R R R R R RW RW R DSP ACCESS TYPE R R RW RW RW RW R R R R R R RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h undef undef undef 0000h 0000h undef 112 SPRS197D August 2002 - Revised August 2004 Functional Overview 3.17 Interrupts Table 3-73. MPU Level 1 and Level 2 Interrupt Mappings INTERRUPT Level 2 Interrupt handler FIQ CAMERA_IF_INTERRUPT Reserved External FIQ McBSP2 TX INT McBSP2 RX INT IRQ_RTDX IRQ_DSP_MMU_ABORT IRQ_HOST_INT IRQ_ABORT IRQ_DSP_MAILBOX1 IRQ_DSP_MAILBOX2 Reserved IRQ_TIPB_BRIDGE_PRIVATE IRQ_GPIO IRQ_UART3 IRQ_TIMER3 IRQ_LB_MMU Reserved IRQ_DMA_CH0_CH6 IRQ_DMA_CH1_CH7 IRQ_DMA_CH2_CH8 IRQ_DMA_CH3 IRQ_DMA_CH4 IRQ_DMA_CH5 IRQ_DMA_CH_LCD IRQ_TIMER1 IRQ_WD_TIMER IRQ_TIPB_BRIDGE_PUBLIC IRQ_LOCAL_BUS_IF IRQ_TIMER2 IRQ_LCD_CTRL FAC KBD MICROWIRE_TX MICROWIRE_RX I2C MPUIO DEFAULT SENSITIVITY Level Level - Edge Edge Edge Level Level Level Level Level Level - Level Level Level Edge Level - Level Level Level Level Level Level Level Edge Edge Level Level Edge Level Level Edge Edge Edge Edge Level LEVEL 1 MAPPING IRQ_0 IRQ_1 IRQ_2 IRQ_3 IRQ_4 IRQ_5 IRQ_6 IRQ_7 IRQ_8 IRQ_9 IRQ_10 IRQ_11 IRQ_12 IRQ_13 IRQ_14 IRQ_15 IRQ_16 IRQ_17 IRQ_18 IRQ_19 IRQ_20 IRQ_21 IRQ_22 IRQ_23 IRQ_24 IRQ_25 IRQ_26 IRQ_27 IRQ_28 IRQ_29 IRQ_30 IRQ_31 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 LEVEL 2 MAPPING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IRQ_0 IRQ_1 IRQ_2 IRQ_3 IRQ_4 IRQ_5 DSP2ARM1 Mailbox Interrupt DSP2ARM2 Mailbox Interrupt Reserved, Keep Masked TIPB Private Bridge Interrupt MPU Interrupt for MPU-Owned Shared GPI UART3 Interrupt MPU Timer 3 Interrupt Local Bus MMU Interrupt Reserved, Keep Masked System DMA Channel 0 and 6 Interrupt System DMA Channel 1 and 7 Interrupt System DMA Channel 2 and 8 Interrupt System DMA Channel 3 Interrupt System DMA Channel 4 Interrupt System DMA Channel 5 Interrupt System DMA LCD Channel Interrupt MPU Timer 1 Interrupt MPU Watchdog Timer Interrupt TIPB Public Bridge Interrupt Local Bus Interrupt MPU Timer 2 Interrupt LCD Controller Interrupt Frame Adjustment Counter Interrupt Keyboard Interrupt MICROWIRE Transmit Interrupt MICROWIRE Receive Interrupt I2C Interrupt MPUIO Interrupt FUNCTION FIQ Interrupt From Level 2 Handler Camera Interface Interrupt Reserved, Keep Masked External FIQ Interrupt McBSP2 Transmit Interrupt McBSP2 Receive Interrupt Real-Time Data Exchange Interrupt (for RTDX Emulation Tools) DSP MMU Abort Interrupt August 2002 - Revised August 2004 SPRS197D 113 Functional Overview Table 3-73. MPU Level 1 and Level 2 Interrupt Mappings (Continued) INTERRUPT USB_HHC1 Reserved Reserved Reserved MCBSP3_TX_INT MCBSP3_RX_INT MCBSP1_TX_INT MCBSP1_RX_INT UART1 UART2 MCSI1_TX_RX_FE_INT MCSI2_TX_RX_FE_INT Reserved Reserved USB_CLNT_GENI_INT 1WIRE_INT TIMER_32K_INT MMC_INT ULPD_INT RTC_PERIODIC_TIMER RTC_ALARM Reserved DSPMMU_IRQ USB_FUNC_IRQ_ISO_ON USB_FUNC_IRQ_NONISO_ON MCBSP2_RX_OVERFLOW_INT DEFAULT SENSITIVITY Level - - - Edge Edge Edge Edge Level Level Level Level - - Level Level Edge Level Level Edge Level - Level Level Level Edge LEVEL 1 MAPPING IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 IRQ_0 LEVEL 2 MAPPING IRQ_6 IRQ_7 IRQ_8 IRQ_9 IRQ_10 IRQ_11 IRQ_12 IRQ_13 IRQ_14 IRQ_15 IRQ_16 IRQ_17 IRQ_18 IRQ_19 IRQ_20 IRQ_21 IRQ_22 IRQ_23 IRQ_24 IRQ_25 IRQ_26 IRQ_27 IRQ_28 IRQ_29 IRQ_30 IRQ_31 DSP MMU Interrupt USB Function Isochronous On Interrupt USB Function Non-Isochronous On Interrupt McBSP2 Receive Overflow Interrupt McBSP3 Transmit Interrupt McBSP3 Receive Interrupt McBSP1 Transmit Interrupt McBSP1 Receive Interrupt UART1 Interrupt UART2 Interrupt MCSI1 Combined Transmit/Receive/Frame Error Interrupt MCSI2 Combined Transmit/Receive/Frame Error Interrupt Reserved, Keep Masked Reserved, Keep Masked USB Function General-Purpose Interrupt 1-Wire Interface Interrupt 32k Timer Interrupt MMC/SD Interrupt Ultra-Low Power Device module Interrupt Real-Time Clock Periodic Timer Interrupt Real-Time Clock Alarm Interrupt FUNCTION USB Host HHC1 Interrupt 114 SPRS197D August 2002 - Revised August 2004 Functional Overview Table 3-74. DSP Level 1 Interrupt Mappings INTERRUPT RESET NMI EMULATOR_TEST LEVEL2_INTH_FIQ TC_ABORT MAILBOX_1 (ARM2DSP1) Reserved GPIO TIMER3 DMA_CHANNEL_1 MPU Reserved UART3 WDGTIMER DMA_CHANNEL_4 DMA_CHANNEL_5 EMIF LOCAL_BUS DMA_CHANNEL_0 MAILBOX2 (ARM2DSP2) DMA_CHANNEL_2 DMA_CHANNEL_3 TIMER2 TIMER1 - - INT2 INT3 INT4 INT5 INT6 INT7 INT8 INT9 INT10 INT11 INT12 INT13 INT14 INT15 INT16 INT17 INT18 INT19 INT20 INT21 INT22 INT23 DSP INTERRUPT DSP IFR/IMR REGISTER BIT - - 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 VECTOR LOCATION (BYTE ADDRESS) FFF00h FFF08h FFF10h FFF18h FFF20h FFF28h FFF30h FFF38h FFF40h FFF48h FFF50h FFF58h FFF60h FFF68h FFF70h FFF78h FFF80h FFF88h FFF90h FFF98h FFFA0h FFFA8h FFFB0h FFFB8h 0 1 3 5 6 7 9 10 11 13 14 15 17 18 21 22 4 8 12 16 19 20 23 24 PRIORITY FUNCTION DSP Reset Interrupt DSP Nonmaskable Interrupt DSP Emulator/Test Interrupt FIQ Interrupt From DSP Level 2 Handler Traffic Controller Abort Interrupt MPU-to-DSP Mailbox 1 Interrupt Unused, Keep Masked Interrupt for DSP-Owned Shared GPIO DSP Timer 3 Interrupt DSP DMA Channel 1 Interrupt MPU Interrupt to DSP Unused, Keep Masked UART Interrupt DSP Watchdog Timer Interrupt DSP DMA Channel 4 Interrupt DSP DMA Channel 5 Interrupt Interrupt for DMA EMIF Interface to Traffic Controller Local Bus Interrupt DSP DMA Channel 0 Interrupt MPU-to-DSP Mailbox 2 Interrupt DSP DMA Channel 2 Interrupt DSP DMA Channel 3 Interrupt DSP Timer 2 Interrupt DSP Timer 1 Interrupt August 2002 - Revised August 2004 SPRS197D 115 Functional Overview Table 3-75. DSP Level 2 Interrupt Mappings INTERRUPT MCBSP3_TX MCBSP3_RX MCBSP1_TX MCBSP1_RX UART2 UART1 MCSI1_TX MCSI1_RX MCSI2_TX MCSI2_RX MCSI1_FRAME_ERROR_INT MCSI2_FRAME_ERROR_INT Reserved Reserved Reserved Reserved DEFAULT SENSITIVITY Edge Edge Edge Edge Level Level Level Level Level Level Level Level - - - - LEVEL 1 MAPPING INT3 INT3 INT3 INT3 INT3 INT3 INT3 INT3 INT3 INT3 INT3 INT3 INT3 INT3 INT3 INT3 LEVEL 2 MAPPING IRQ_0 IRQ_1 IRQ_2 IRQ_3 IRQ_4 IRQ_5 IRQ_6 IRQ_7 IRQ_8 IRQ_9 IRQ_10 IRQ_11 IRQ_12 IRQ_13 IRQ_14 IRQ_15 FUNCTION McBSP3 Transmit Interrupt McBSP3 Receive Interrupt McBSP1 Transmit Interrupt McBSP1 Receive Interrupt UART2 Interrupt UART1 Interrupt MCSI1 Transmit Interrupt MCSI1 Receive Interrupt MCSI2 Transmit Interrupt MCSI2 Receive Interrupt MCSI1 Frame Error Interrupt MCSI2 Frame Error Interrupt Reserved, Keep Masked Reserved, Keep Masked Reserved, Keep Masked Reserved, Keep Masked 116 SPRS197D August 2002 - Revised August 2004 Functional Overview 3.18 MPU System DMA Request Mapping Table 3-76 shows the MPU system DMA request mapping for the OMAP5910 device. Table 3-76. DMA Request Mapping MPU SYSTEM DMA REQUESTS MCSI1 TX MCSI1 RX I2C RX I2C TX EXT_DMA_REQ0 (MPUIO2) EXT_DMA_REQ1 (MPUIO4) MicroWire TX McBSP1 TX McBSP1 RX McBSP3 TX McBSP3 RX UART1 TX UART1 RX UART2 TX UART2 RX McBSP2 TX McBSP2 RX UART3 TX UART3 RX Camera RX MMC TX MMC RX Reserved Reserved Reserved USB function RX0 USB function RX1 USB function RX2 USB function TX0 USB function TX1 USB function TX2 MPU SYSTEM DMA DMA_REQ_01 DMA_REQ_02 DMA_REQ_03 DMA_REQ_04 DMA_REQ_05 DMA_REQ_06 DMA_REQ_07 DMA_REQ_08 DMA_REQ_09 DMA_REQ_10 DMA_REQ_011 DMA_REQ_012 DMA_REQ_013 DMA_REQ_014 DMA_REQ_015 DMA_REQ_016 DMA_REQ_017 DMA_REQ_018 DMA_REQ_019 DMA_REQ_020 DMA_REQ_021 DMA_REQ_022 DMA_REQ_023 DMA_REQ_024 DMA_REQ_025 DMA_REQ_026 DMA_REQ_027 DMA_REQ_028 DMA_REQ_029 DMA_REQ_030 DMA_REQ_031 August 2002 - Revised August 2004 SPRS197D 117 Functional Overview 3.19 DSP DMA Event Mapping Table 3-77 defines the mappings of the DMA channel synchronization settings to the different request sources that can be used to create DSP DMA events on OMAP5910. Table 3-77. DSP DMA Mapping DSP REQUEST SOURCE MCSI1 TX MCSI1 RX MCSI2 TX MCSI2 RX EXT_DMA_REQ0 (MPUIO2) EXT_DMA_REQ1 (MPUIO4) Reserved McBSP1 TX McBSP1 RX McBSP3 TX McBSP3 RX UART1 TX UART1 RX UART2 TX UART2 RX Reserved Reserved UART3 TX UART3 RX DSP DMA REQUEST LINE DMA_REQ_01 DMA_REQ_02 DMA_REQ_03 DMA_REQ_04 DMA_REQ_05 DMA_REQ_06 DMA_REQ_07 DMA_REQ_08 DMA_REQ_09 DMA_REQ_10 DMA_REQ_011 DMA_REQ_012 DMA_REQ_013 DMA_REQ_014 DMA_REQ_015 DMA_REQ_016 DMA_REQ_017 DMA_REQ_018 DMA_REQ_019 118 SPRS197D August 2002 - Revised August 2004 Documentation Support 4 Documentation Support Extensive documentation supports all OMAP platform of devices from product announcement through applications development. The following types of documentation are available to support the design and use of the OMAP platform of dual-core processor devices: * * * Device-specific data sheets Development-support tools Hardware and software application reports The OMAP5910 reference documentation includes, but is not limited to, the following: * * * * * * * * * * * * * * * * * * * * * * * TMS320C55x DSP CPU Programmer's Reference Supplement (literature number SPRU652) OMAP5910 Dual-Core Processor Functional and Peripheral Overview (literature number SPRU602) OMAP5910 Dual-Core Processor MPU Subsystems Reference Guide (literature number SPRU671) OMAP5910 Dual-Core Processor DSP Subsystems Reference Guide (literature number SPRU672) OMAP5910 Dual-Core Processor Memory Interface Traffic Controller Reference Guide (literature number SPRU673) OMAP5910 Dual-Core Processor System DMA Controller Reference Guide (literature number SPRU674) OMAP5910 Dual-Core Processor LCD Controller Reference Guide (literature number SPRU675) OMAP5910 Dual-Core Processor Universal Asynchronous Receiver/Transmitter (UART) Devices Reference Guide (literature number SPRU676) OMAP5910 Dual-Core Processor Universal Serial Bus (USB) and Frame Adjustment Counter (FAC) Reference Guide (literature number SPRU677) OMAP5910 Dual-Core Processor Clock Generation and System Reset Management Reference Guide (literature number SPRU678) OMAP5910 Dual-Core Processor General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU679) OMAP5910 Dual-Core Processor MultiMedia Card/Secure Data Memory Card (MMC/SD) Reference Guide (literature number SPRU680) OMAP5910 Dual-Core Processor Inter-Integrated Circuit (I 2C) Controller Reference Guide (literature number SPRU681) OMAP5910 Dual-Core Processor Timer Reference Guide (literature number SPRU682) OMAP5910 Dual-Core Processor Inter-Processor Communication Reference Guide (literature number SPRU683) OMAP5910 Dual-Core Processor Camera Interface Reference Guide (literature number SPRU684) OMAP5910 Dual-Core Processor Multichannel Serial Interface (MCSI) Reference Guide (literature number SPRU685) OMAP5910 Dual-Core Processor MicroWire Interface Reference Guide (literature number SPRU686) OMAP5910 Dual-Core Processor Real-Time Clock (RTC) Reference Guide (literature number SPRU687) OMAP5910 Dual-Core Processor HDQ/1-Wire Interface Reference Guide (literature number SPRU688) OMAP5910 Dual-Core Processor PWL, PWT, and LED Reference Guide (literature number SPRU689) OMAP5910 Dual-Core Processor Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU708) OMAP5910 Dual-Core Processor Silicon Errata (literature number SPRZ016) A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 DSP customers on product information. Information regarding Texas Instruments (TI) OMAP and DSP products is also available on the Worldwide Web at http://www.ti.com uniform resource locator (URL). TMS320 and TMS320C5000 are trademarks of Texas Instruments. August 2002 - Revised August 2004 SPRS197D 119 Documentation Support 4.1 Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all OMAP processors and support tools. Each commercial OMAP platform member has one of three prefixes: X, P, or null (no prefix). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMDX) through fully qualified production devices/tools (TMDS). Device development evolutionary flow: X Experimental device that is not necessarily representative of the final device's electrical specifications and may not use production assembly flow. (TMX definition) Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications. (TMP definition) Production version of the silicon die that is fully qualified. (TMS definition) P null Support tool development evolutionary flow: TMDX Development support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." Production devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X or P), have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. For additional description of the device nomenclature markings, see the OMAP5910 Dual-Core Processor Silicon Errata (literature number SPRZ016). P OMAP 5910 X GZG S PREFIX X P null Experimental device Prototype device Production device DEVICE SILICON REVISION TEMPERATURE RANGE NULL = - 40C to 85C Case C = 0C to 85C Case SPEED GRADE 2 = 150 MHz PACKAGE GZG = ZZG = GDY = TYPE 289-pin MicroStar BGA Lead-Free 289-pin MicroStar BGA 289-pin BGA Figure 4-1. OMAP Device Nomenclature 120 SPRS197D August 2002 - Revised August 2004 Electrical Specifications 5 Electrical Specifications This section provides the absolute maximum ratings and the recommended operating conditions for the OMAP5910 device. All electrical and switching characteristics in this data manual are valid over the recommended operating conditions unless otherwise specified. 5.1 Absolute Maximum Ratings The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.2, Recommended Operating Conditions, is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All supply voltage values (core and I/O) are with respect VSS. NOTE: The OMAP5910 device has undergone Charged Device Model Electrostatic Discharge (ESD) testing, passing at the 500 V level. Human Body Model (HBM) ESD testing per EIA/JESD22-A114 has also been performed. Test results indicate that the OMAP5910 passes at a 500 V HBM (maximum) level. Caution in handling devices is advised. This section provides the absolute maximum ratings for the OMAP5910 device. Supply voltage range (core), CVDD,CVDD1/2/3/4/A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 1.8 V Supply voltage range (I/O), DVDD1/2/3/4/5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Input voltage range, VI (12-MHz and 32-kHz oscillator) . . . . . . . . . . . . . . . . . . . . . -0.3 V to CVDD + 0.5 V Input voltage range, VI (standard LVCMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to DVDD + 0.5 V Input voltage range, VI (fail-safe LVCMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4.5 V Input voltage range, VI (USB transceivers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to DVDD + 0.5 V Input voltage range, VI (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4.5 V Output voltage range, VO (standard LVCMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to DVDD + 0.5 V Output voltage range, VO (fail-safe LVCMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4.5 V Output voltage range, VO (USB transceivers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to DVDD + 0.5 V Output voltage range, VO (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4.5 V Operating temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 150C August 2002 - Revised August 2004 SPRS197D 121 Electrical Specifications 5.2 Recommended Operating Conditions MIN NOM 1.1 1.6 2.75 or 3.3 3.3 1.8 2.75 or 3.3 1.8 2.75 or 3.3 1.8 2.75 or 3.3 MAX 1.675 1.675 3.6 3.6 1.95 3.6 1.95 3.6 2 3.6 1.65 2.6 0 Standard LVCMOS 0.7 DVDD 0.7 DVDD 2 0.7 DVDD 0 0 0 0 0.8 200 -2 -4 -8 -18.3 2 4 6 8 18.3 -40 85 C mA mA DVDD DVDD DVDD DVDD 0.3 DVDD 0.3 DVDD 0.8 0.3 DVDD 2.5 CVDD V mV V V Fail-safe LVCMOS USB.DP, DM (mode 1) I2C Standard LVCMOS Fail-safe LVCMOS USB.DP, DM (mode 1) I2C USB.DP, DM (mode 2) OSC1 and OSC32K pins USB.DP, DM (mode 2) 2-mA drive strength buffers 4-mA drive strength buffers UNIT V V V V V V V V V Device supply voltage, core voltage Low Power Standby mode Active mode 1 1.525 2.5 3 range 1.65 2.5 1.65 2.5 1.65 2.5 CVDD CVDD1/2/3/4/A DVDD1 DVDD2 DVDD3 DVDD4 DVDD5 CVDD - DVDD DVDD - CVDD VSS Device supply voltage, I/O (Peripheral I/O) Device supply voltage, I/O (USB transceiver) Device supply voltage, I/O (MCSI2, McBSP2, GPIO[9:8]) Device supply voltage, I/O (SDRAM interface) Device supply voltage, I/O (FLASH interface) Device supply voltage difference Device supply voltage difference Supply voltage, GND Low-voltage High-voltage range Low-voltage range High-voltage range Low-voltage range High-voltage range VIH High-level High level input voltage I/O voltage, VIL Low-level Low level input voltage I/O voltage, VI VID Input voltage Differential input voltage, I/O IOH High-level output current g p 8-mA drive strength buffers 18.3-mA drive strength buffers 2-mA drive strength buffers 4-mA drive strength buffers 6-mA drive strength buffers 8-mA drive strength buffers 18.3-mA drive strength buffers IOL Low-level output current TC Operating case temperature All core voltage supplies should be tied to the same voltage level (within 0.3 V). Low Power Standby is defined as follows: the device is in Deep Sleep mode and LOW_PWR = 1. The device runs from 32 kHz clock in this mode. High and low voltage ranges are selectable via software configuration. In systems where the CV DDx and DVDDx power supplies are ramped at generally the same time (within 500 ms of one another), there are no specific power sequencing requirements for the supplies. The only sequencing requirement is that the maximum voltage difference between CVDD and DVDD is not exceeded for greater than 500 ms. Likewise, if different voltages are used for the separate DVDDx supplies, all DVDDx supplies should be ramp up to valid voltage levels within 500 ms of one another. 122 SPRS197D August 2002 - Revised August 2004 Electrical Specifications 5.3 Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted) PARAMETER TEST CONDITIONS DVDD = 3.3 V, IOH = MAX DVDD = 3.3 V, IOH = MAX IO = -12 mA DVDD = 3.3 V, IOL = MAX DVDD = 3.3 V, IOL = MAX IO = 12 mA Fast mode at 6-mA load I2C Fast mode at 3-mA load Standard mode at 3-mA load VI = VI MAX to VI MIN VI = VI MAX to VI MIN DVDD = MAX, VI = VSS to VDD DVDD = MAX, VI = VSS to VDD CVDD = MAX, VI = VSS to VDD DVDD = MAX, VI = VSS to VDD Sum of CVDDx currents. (Deep sleep mode with CVDD = 1.6 V) Sum of CVDDx currents. (Deep sleep mode with CVDD = 1.1 V) Sum of CVDDx currents (Case 1). Sum of CVDDx currents (Case 2). Sum of CVDDx and DVDDx currents (Case 3). Sum of CVDDx and DVDDx currents (Case 4). USB.DP,DM All other I/O pins USB.DP,DM All other I/O pins - 20 -1 6 30 - 60 - 300 - 20 210 A 110 20 100 - 20 - 100 MIN 0.8 DVDD 0.8 DVDD DVDD - 0.5 0.22 DVDD 0.22 DVDD 0.5 0.6 0.4 0.4 V V TYP MAX UNIT High-level output Hi h l ltt voltage Standard LVCMOS Fail-safe LVCMOS USB.DP, DM Standard LVCMOS Fail-safe LVCMOS USB.DP, DM VOH VOL Low-level Low level output voltage Fail-safe LVCMOS inputs without internal pullups/pulldowns enabled Other Inputs without internal pullups/pulldowns enabled II Input current Input pins with 20-A pulldowns enabled Input pins with 100-A pulldowns enabled Input pins with 20-A pullups enabled Input pins with 100-A pullups enabled IOZ Input current for outputs in high-impedance 20 1 60 300 -6 - 30 20 A A IDDC (Q) Core voltage supply current quiescent current, 150 170 45 6 7 4 7 4 mA mA mA mA pF pF IDDC (A) Core voltage supply current active current, IDDCP (A) Core and I/O voltage supply current active current, Ci CO Input capacitance Output capacitance Case 1: MPU running OS, DSP running GSM Vocoder from internal memory, DSP MMU and all clock domains active, no LCD activity. Case 2: Same conditions as Case 1 only DSP running from external memory with I-cache enabled. Case 3: Only LCD activity (MPU and DSP idled with clocks off). LCD running 320x240 TFT at 70 Frames per second with frame buffer in internal memory (DPLL at 120 MHz). Case 4: Same as Case 3 only LCD running at 10 Frames per second with DPLL at 6MHz. August 2002 - Revised August 2004 SPRS197D 123 Electrical Specifications Tester Pin Electronics Data Sheet Timing Reference Point 42 W 3.5 nH Transmission Line Z0 = 50 W (see note) Output Under Test Device Pin (see note) 4.0 pF 1.85 pF NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure 5-1. Tester Pin Electronics 5.4 Package Thermal Resistance Characteristics Table 5-1 provides the thermal resistance characteristics for the package types available for use on the OMAP5910 device. Table 5-1. Thermal Resistance Characteristics RJA (C / W) 32.77 25.54 RJC (C / W) 10.76 10.11 PACKAGE TYPE 289GZG 289GDY 5.5 Timing Parameter Symbology Timing parameter symbols used in the timing requirements and switching characteristics tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: Lowercase subscripts and their meanings: a c d dis en f h r su t v w X access time cycle time (period) delay time disable time enable time fall time hold time rise time setup time transition time valid time pulse duration (width) Unknown, changing, or don't care level Letters and symbols and their meanings: H L V Z High Low Valid High impedance 124 SPRS197D August 2002 - Revised August 2004 Electrical Specifications 5.6 Clock Specifications This section provides the timing requirements and switching characteristics for the OMAP5910 system clock signals. 5.6.1 32-kHz Oscillator and Input Clock The 32.768-kHz clock signal (often abbreviated to 32-kHz) may be supplied by either the on-chip 32-kHz oscillator (requiring an external crystal) or an external CMOS signal. The state of the CLK32K_CTRL pin determines which is used. The on-chip oscillator requires an external 32.768-kHz crystal connected across the OSC32K_IN and OSC32K_OUT pins. The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 5-2. The load capacitors, C1 and C2, should be chosen such that the equation below is satisfied (recommended values are C1 = C2 = 10 pF). CL in the equation is the load specified for the crystal. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (OSC32K_IN and OSC32K_OUT) and to the VSS pin closest to the oscillator pins (GZG ball V12 or GDY ball F6). NOTE: The 32.768-kHz oscillator is powered by the CVDD supply. If an external clock source is used instead of using the on-chip oscillator, care must be taken that the voltage level driven onto the OSC32K_IN and OSC32K_OUT pins is no greater than the CVDD voltage level. C 1C 2 (C 1 ) C 2) CL + OSC32K_IN OSC32K_OUT VSS Crystal 32.768 kHz C1 C2 Figure 5-2. 32-kHz Oscillator External Crystal Table 5-2 shows the switching characteristics of the 32-kHz oscillator and Table 5-3 shows the input requirements of the 32-kHz clock input. Table 5-2. 32-kHz Oscillator Switching Characteristics PARAMETER Start-up time (from power up until oscillating at stable frequency of 32.768 kHz) IDDA, active current consumption Oscillation frequency MIN TYP 200 4 32.768 MAX 800 UNIT ms A kHz August 2002 - Revised August 2004 SPRS197D 125 Electrical Specifications Table 5-3. 32-kHz Input Clock Timing Requirements NO. CK1 CK2 CK3 CK4 CK5 tcyc tf tr Frequency Fall time Rise time Duty cycle (high-to-low ratio) Frequency stability 30% -70 CK3 CK1 CK2 MIN NOM 32.768 25 25 70% 70 MAX UNIT kHz ns ns % ppm CLK32K_IN Figure 5-3. 32-kHz Input Clock 5.6.2 Base Oscillator (12 MHz or 13 MHz) and Input Clock The internal base system oscillator is enabled following a device reset. The oscillator requires an external crystal to be connected across the OSC1_IN and OSC1_OUT pins. If the internal oscillator is not used (configured in software using FUNC_MUX_CTRL_B register), an external clock source must be applied to the OSC1_IN pin and the OSC1_OUT pin must be left unconnected. Because the internal oscillator can be used as a clock source to the OMAP DPLL, the 12- or 13-MHz crystal oscillation frequency can be multiplied to generate the DSP clock, MPU clock, traffic controller clock. The crystal must be in fundamental-mode operation, and parallel resonant, with a maximum effective series resistance of 60 maximum. The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 5-4. The load capacitors, C1 and C2, must be chosen such that the equation below is satisfied (recommended values are C1 = C2 = 10 pF). CL in the equation is the load specified for the crystal. All discrete components used to implement the oscillator circuit must be placed as close as possible to the associated oscillator pins (OSC1_IN and OSC1_OUT) and to the VSS pins closest to the oscillator pins (GZG balls AA1/Y3 or GDY balls E13/K9). NOTE: The base oscillator is powered by the CVDD supply. If an external clock source is used instead of using the on-chip oscillator, care must be taken that the voltage level driven onto the OSC1_IN pin is no greater than the CVDD voltage level. CL + C 1C 2 (C 1 ) C 2) OSC1_IN OSC1_OUT 12 or 13 MHz crystal C1 C2 Figure 5-4. Internal System Oscillator External Crystal 126 SPRS197D August 2002 - Revised August 2004 Electrical Specifications If USB host function is used, it is recommended that a very low PPM crystal ( 50 ppm) be used for the 12- or 13-MHz oscillator circuit. If the USB host function is not used, then a crystal of 180 ppm is recommended. When selecting a crystal, the system design must take into account the temperature and aging characteristics of a crystal versus the user environment and expected lifetime of the system. Table 5-4 shows the switching characteristics of the base oscillator. Table 5-4. Base Oscillator Switching Characteristics PARAMETER Start-up time (from power up until oscillating at stable frequency of 12 or 13 MHz) IDDA, active current consumption Oscillation frequency MIN TYP 1 350 12 or 13 MAX 4 UNIT ms A MHz 5.6.3 Internal Clock Speed Limitations Table 5-5 provides a summary of the maximum frequencies that each clock domain may be configured to run on the OMAP5910 device. Table 5-5. Internal Clock Speed Limitations CLOCK MPU (CLKM1) DSP (CLKM2) TC (CLKM3) DPLL1 MAX OPERATING FREQUENCY 150 150 75 150 UNIT MHz MHz MHz MHz All clock domains must be derived from the same DPLL1 frequency setting; therefore, the following conditions must be satisfied where `m', `n', and `o' are each equal to either 1, 2, 4, or 8: * * * MPU frequency = (DPLL1 clock frequency) / m DSP frequency = (DPLL1 clock frequency) / n TC frequency = (DPLL1 clock frequency) / o For example, the following configuration is valid: * MPU/DSP/TC = 150 MHz/150 MHz/75 MHz, where m = n = 1 and o = 2 August 2002 - Revised August 2004 SPRS197D 127 Electrical Specifications 5.7 Reset Timings This section provides the timing requirements for the OMAP5910 hardware reset signals. 5.7.1 OMAP5910 Device Reset The PWRON_RESET signal is the active-low asynchronous reset input responsible for the reset of the entire OMAP5910 device. When using an external crystal to supply the 32-kHz system clock, PWRON_RESET must be asserted low a minimum of two 32-kHz clock cycles longer than the worst-case start-up time of the 32-kHz oscillator after stable power supplies (see Figure 5-5). If an external CMOS input signal is used to source 32 kHz, PWRON_RESET must be asserted low a minimum of two 32-kHz clock cycles after stable power supplies. See Table 5-6 and Table 5-7. Table 5-6. OMAP5910 Device Reset Timing Requirements NO. RS1 tw(PWRON_RST) Pulse duration, PWRON_RESET low MIN 800 MAX UNIT ms Table 5-7. OMAP5910 Device Reset Switching Characteristics NO. RS2 PARAMETER td(PWRONH-RSTH) Delay time, PWRON_RESET high to RST_OUT high MIN MAX T + 10 UNIT s P = period of 32-kHz clock, C = Value of ULPD wakeup time setup register, SETUP_ULPD1_REG (Default 03FFh), T = P*C CVDDx DVDDx RS1 Worst-case Oscillator Start-up Time OSC32K_IN 2 Cycles PWRON_RESET RS2 RST_OUT Figure 5-5. Device Reset Timings 128 SPRS197D August 2002 - Revised August 2004 Electrical Specifications 5.7.2 OMAP5910 MPU Core Reset The MPU_RST signal is the active-low asynchronous input responsible for the reset of the OMAP5910 MPU core. Stable power supplies are assumed prior to MPU_RST assertion. Table 5-6 illustrates the behavior of MPU_RST and RST_OUT. In Table 5-7, a logic high level is assumed on the PWRON_RESET input. In the case where an application ties the PWRON_RESET and MPU_RST together, the behavior described in Section 5.7.1, OMAP5910 Device Reset, will override. See Table 5-8 and Table 5-9. Table 5-8. MPU_RST Timing Requirements NO. M3 tw(MPU_RST) Pulse duration, MPU_RST low MIN 50 MAX UNIT s Table 5-9. MPU_RST Switching Characteristics NO. M1 td(MPUL-RSTL) PARAMETER Delay time, MPU_RST low to RST_OUT low MPU_RST asserted during OMAP5910 awake state MPU_RST asserted during OMAP5910 deep sleep state MIN MAX 1 10 s T + 10 UNIT s M2 td(MPUH-RSTH) Delay time MPU RST high to RST OUT high time, MPU_RST RST_OUT P = period of 32-kHz clock, C = Value of ULPD wakeup time setup register, SETUP_ULPD1_REG (Default 03FFh), T = P*C M3 MPU_RST M1 RST_OUT M2 Figure 5-6. MPU Core Reset Timings August 2002 - Revised August 2004 SPRS197D 129 Electrical Specifications 5.8 External Memory Interface Timing Table 5-10 and Table 5-11 assume testing over recommended operating conditions (see Figure 5-7 through Figure 5-11). Table 5-10. EMIFS/Flash Interface Timing Requirements 5.8.1 EMIFS/Flash Interface Timing NO. Setup time, read data valid before FLASH.CLK high Hold time, read data valid after FLASH.CLK high Async modes Sync Modes Async modes Sync Modes DVDD5 = 1.8 V Nominal MIN MAX 9 3 0 2 DVDD5 = 2.75 V Nominal MIN 9 3 0 2 MAX DVDD5 = 3.3 V Nominal MIN 9 3 0 2 MAX UNIT ns ns ns ns F6 F7 tsu(DV-CLKH) th(CLKH-RDV) The external FLASH.CLK is disabled for async modes. Async modes are only supported with the RT bit in the EMIFS configuration register set to 0. Sync modes are only supported with the RT bit in the EMIFS configuration register set to 1. 130 SPRS197D August 2002 - Revised August 2004 Electrical Specifications Table 5-11. EMIFS/Flash Interface Switching Characteristics DVDD5 = 1.8 V Nominal MIN Delay time, FLASH.CLK high to FLASH.CSx transition Delay time, FLASH.CLK high to FLASH.BEx valid Delay time, FLASH.CLK high to FLASH.BEx invalid Delay time, FLASH.CLK FLASH CLK high to address valid Delay time, FLASH.CLK FLASH CLK high to address invalid Delay time, FLASH.CLK high to FLASH.ADV transition Delay time, FLASH.CLK high to FLASH.OE transition Delay time, FLASH.CLK high to FLASH.WE transition Delay time, FLASH.CLK FLASH CLK high to write data valid Delay time, FLASH.CLK high to write data invalid Async Modes Sync Modes Async Modes Sync Modes Async Modes Sync Modes Async Modes Sync Modes Async Modes Sync Modes Async Modes Sync Modes Async Modes Sync Modes Async Modes Sync Modes Async Modes Sync Modes Async Modes Sync Modes 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 1 1 1 MAX 24 12 24 12 24 12 24 8 24 8 24 12 24 12 24 12 24 22 24 22 24 1 -1 + 0.5P 24 8 + 0.5P 1 -1 + 0.5P DVDD5 = 2.75 V Nominal MIN 1 -1 1 -1 1 -1 1 0 1 0 1 -1 1 -1 1 -1 1 1 1 1 MAX 21 10 21 10 21 10 21 7 21 7 21 10 21 10 21 10 21 20 21 20 21 21 7.5 + 0.5P 1 -1 + 0.5P DVDD5 = 3.3 V Nominal MIN 1 -1 1 -1 1 -1 1 0 1 0 1 -1 1 -1 1 -1 1 1 1 1 MAX 11 ns 11 20 ns 11 20 ns 11 20 ns 7 20 ns 7 20 ns 11 20 ns 11 20 ns 11 20 ns 18 20 ns 18 20 20 7.5 + 0.5P ns ns ns NO. PARAMETER UNIT F1 td(CLKH-CSV) F2 td(CLKH-BEV) F3 td(CLKH-BEIV) F4 td(CLKH-AV) F5 td(CLKH-AIV) F8 td(CLKH-ADV) F9 td(CLKH-OEV) F12 td(CLKH-WEV) F13 td(CLKH-WDV) F14 td(CLKH-WDIV) F15 F16 F17 td(CLKH-DHZ) td(CLKH-DLZ) td(CLKH-BAAV) Delay time, FLASH.CLK high to data bus high-impedance Delay time, FLASH.CLK high to data bus driven Delay time, FLASH.CLK high to FLASH.BAA transition Data is referenced to the internal FLASH.CLK. The external FLASH.CLK is disabled for async modes. P = period of undivided Traffic Controller clock regardless of FLASH.CLK divider configuration August 2002 - Revised August 2004 SPRS197D 131 Electrical Specifications N cycles FLASH.CLK (internal) F1 FLASH.CSx F2 FLASH.BE[1:0] F4 FLASH.A[24:1] A1 F6 FLASH.D[15:0] F8 FLASH.ADV F9 FLASH.OE FLASH.WE F1 F3 Valid F5 F7 D1 F8 F9 FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to express relative timings. Number of cycles is configurable via EMIFS setup registers. Figure 5-7. Asynchronous Memory Read Timing 132 SPRS197D August 2002 - Revised August 2004 Electrical Specifications M cycles F1 FLASH.CSx F2 FLASH.BE[1:0] F4 FLASH.A[24:1] F6 FLASH.D[15:0] F8 FLASH.ADV F9 FLASH.OE FLASH.WE N cycles FLASH.CLK (internal) F1 F3 Valid F5 A1 F7 D1 lower F6 D1 upper F8 F9 F7 FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to express relative timings. Number of cycles is configurable via EMIFS setup registers. Figure 5-8. Asynchronous 32-Bit Read August 2002 - Revised August 2004 SPRS197D 133 Electrical Specifications P cycles M FLASH.CLK (internal) F1 FLASH.CSx F2 FLASH.BE[1:0] F4 FLASH.A[24:3] F4 FLASH.A[2:1] Word 0 F6 FLASH.D[15:0] F8 FLASH.ADV F9 FLASH.OE FLASH.WE FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to express relative timings. Number of cycles is configurable via EMIFS setup registers. F9 D1 F5 F4 Word 1 F7 D2 D3 Word 2 Word 3 F6 D4 F8 F7 A1 F5 Valid F5 F3 F1 cycles P cycles P cycles Figure 5-9. Asynchronous Read - Page Mode ROM 134 SPRS197D August 2002 - Revised August 2004 Electrical Specifications ADV width N cycles FLASH.CLK (internal) F1 FLASH.CSx F2 FLASH.BE[1:0] F4 FLASH.A[24:1] F16 FLASH.D[15:0] F8 FLASH.ADV FLASH.OE FLASH.WE Wait-states M cycles WE width P cycles CS hold Q cycles F1 F3 Valid F5 A1 F13 D1 F8 F15 F14 F12 F12 FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to express relative timings. Number of cycles is configurable via EMIFS setup registers. Figure 5-10. Asynchronous Memory Write Timing August 2002 - Revised August 2004 SPRS197D 135 Electrical Specifications ADV width N cycles CLK start Q cycles FLASH.CLK (external) FLASH.CSx F2 FLASH.BE[1:0] F4 FLASH.A[24:1] A1 F6 FLASH.D[15:0] F8 FLASH.ADV F17 FLASH.BAA F9 FLASH.OE FLASH.WE F9 F17 F8 D1 F7 D2 F6 D3 D4 F7 Valid F5 F3 F1 Wait-states M cycles F1 FLASH.CLK is only driven during the active portion of the cycle. For reference, the dashed line shows FLASH.CLK as if it were continuous. Number of cycles is configurable via EMIFS setup registers. Figure 5-11. Synchronous Burst Read 136 SPRS197D August 2002 - Revised August 2004 Electrical Specifications 5.8.2 EMIFF/SDRAM Interface Timing Table 5-12 and Table 5-13 assume testing over recommended operating conditions (see Figure 5-12 through Figure 5-17). Table 5-12. EMIFF/SDRAM Interface Timing Requirements NO. Setup time, read data valid before SDRAM.CLK high Hold time, read data valid after SDRAM.CLK high DVDD4 = 1.8 V Nominal MIN SD7 SD8 DVDD4 = 2.75 V Nominal MIN 2 1 MAX DVDD4 = 3.3 V Nominal MIN 2 1 MAX UNIT MAX tsu(DV-CLKH) th(CLKH-DV) 2 1 ns ns Timing requirements are with the SD_RET field equal to 1 in the EMIFF configuration register. Table 5-13. EMIFF/SDRAM Interface Switching Characteristics NO. SD1 SD2 SD3 SD4 SD5 SD6 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SD16 SD17 SD18 PARAMETER tc(CLK) tw(CLK) td(CLKH-DQMV) td(CLKH-DQMIV) td(CLKH-AV) td(CLKH-AIV) td(CLKH-SDCASL) td(CLKH-SDCASH) td(CLKH-DV) td(CLKH-DIV) td(CLKH-SDWEL) td(CLKH-SDWEH) td(CLKH-BAV) td(CLKH-BAIV) td(CLKH-RASL) td(CLKH-RASH) Cycle time, SDRAM.CLK Pulse duration, SDRAM.CLK high/low Delay time, SDRAM.CLK high to SDRAM.DQMx valid Delay time, SDRAM.CLK high to SDRAM.DQMx invalid Delay time, SDRAM.CLK high to SDRAM.A[12:0] address valid Delay time, SDRAM.CLK high to SDRAM.A[12:0] address invalid Delay time, SDRAM.CLK high to SDRAM.CAS low Delay time, SDRAM.CLK high to SDRAM.CAS high Delay time, SDRAM.CLK high to SDRAM.D[15:0] data valid Delay time, SDRAM.CLK high to SDRAM.D[15:0] data invalid Delay time, SDRAM.CLK high to SDRAM.WE low Delay time, SDRAM.CLK high to SDRAM.WE high Delay time, SDRAM.CLK high to SDRAM.BA[1:0] valid Delay time, SDRAM.CLK high to SDRAM.BA[1:0] invalid Delay time, SDRAM.CLK high to SDRAM.RAS low Delay time, SDRAM.CLK high to SDRAM.RAS high DVDD4 = 1.8 V Nominal MIN H 2.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 9 9 9 9 9 9 9 9 9 9 9 9 9 9 MAX DVDD4 = 2.75 V Nominal MIN H 2.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 9 9 9 9 9 9 9 9 9 9 9 9 9 9 MAX DVDD4 = 3.3 V Nominal MIN H 2.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 9 9 9 9 9 9 9 9 9 9 9 9 9 9 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns H = 1/2 CPU cycle. August 2002 - Revised August 2004 SPRS197D 137 Electrical Specifications READ SDRAM.CLK SD2 SDRAM.CKE SD3 SDRAM.DQMx SD5 SDRAM.A[12:0] SDRAM.BA[1:0] CA1 SD15 Bank Address SD7 SDRAM.D[15:0] SDRAM.RAS SDRAM.CAS SDRAM.WE D1 SD8 D2 SD6 CA2 SD16 SD2 SD1 READ BURST TERMINATE SD9 SD10 Figure 5-12. 32-Bit (2 x 16-Bit) SDRAM RD (Read) Command (Active Row) WRITE SDRAM.CLK SDRAM.CKE SD3 SDRAM.DQMx SDRAM.A[12:0] SDRAM.BA[1:0] SDRAM.D[15:0] SDRAM.RAS SD9 SDRAM.CAS SDRAM.WE SD13 SD14 SD11 D1 BE1 SD15 CA1 SD15 Bank Address SD12 D2 SD4 BE2 SD16 CA2 WRITE BURST TERMINATE SD16 SD10 Figure 5-13. 32-Bit (2 x 16-Bit) SDRAM WRT (Write) Command (Active Row) 138 SPRS197D August 2002 - Revised August 2004 Electrical Specifications ACTV SDRAM.CLK SDRAM.CKE SDRAM.DQMx SD5 SDRAM.A[12:0] SD15 SDRAM.BA[1:0] SDRAM.D[15:0] SD17 SDRAM.RAS SDRAM.CAS SDRAM.WE SD18 Bank Activate Row Address Figure 5-14. SDRAM ACTV (Activate Row) Command DCAB SDRAM.CLK SDRAM.CKE SDRAM.DQMx SDRAM.A[12:11, 9:0] SDRAM.BA[1:0] SDRAM.D[15:0] SD5 SDRAM.A[10] SD17 SDRAM.RAS SDRAM.CAS SD13 SDRAM.WE SD14 SD18 SD6 Figure 5-15. SDRAM DCAB (Precharge/Deactivate Row) Command August 2002 - Revised August 2004 SPRS197D 139 Electrical Specifications REFR SDRAM.CLK SDRAM.CKE SDRAM.DQMx SDRAM.A[12:11, 9:0] SDRAM.BAx SDRAM.D[15:0] SDRAM.A[10] SDRAM.RAS SD9 SDRAM.CAS SDRAM.WE SD10 SD5 SD17 SD6 SD18 Figure 5-16. SDRAM REFR (Refresh) Command MRS SDRAM.CLK SDRAM.CKE SDRAM.DQMx SD5 SDRAM.A[9:0] SDRAM.BA[1:0] SDRAM.D[15:0] SD5 SDRAM.A10 SD17 SDRAM.RAS SD9 SDRAM.CAS SD13 SDRAM.WE SD14 SD10 SD18 SD6 MRS Value SD6 Figure 5-17. SDRAM MRS (Mode Register Set) Command 140 SPRS197D August 2002 - Revised August 2004 Electrical Specifications 5.9 Multichannel Buffered Serial Port (McBSP) Timings Table 5-14 and Table 5-15 assume testing over recommended operating conditions (see Figure 5-18 and Figure 5-19). In Table 5-14 and Table 5-15, "ext" indicates that the device pin is configured as an input (slave) driven by an external device and "int" indicates that the pin is configured as an output (master). Table 5-14. McBSP Timing Requirements 5.9.1 McBSP Transmit and Receive Timings NO. M11 M12 tc(CKRX) tw(CKRX) Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low McBSP1 M13 tr Rise time, CLKR/X, MCBSP2.FSR/X McBSP2 McBSP3 McBSP1 M14 tf Fall time, CLKR/X, MCBSP2.FSR/X McBSP2 McBSP3 McBSP1 (FSX) M15 tsu(FRH-CKRL) Setup time, external receiver frame sync (FSR/X) high before CLKR/X low McBSP2 (FSR) McBSP3 (FSX) McBSP1 (FSX) M16 th(CKRL-FRH) Hold time, external receiver frame sync (FSR/X) high after CLKR/X low McBSP2 (FSR) McBSP3 (FSX) McBSP1 M17 tsu(DRV-CKRL) Setup time DR valid before CLKR/X low time, McBSP2 McBSP3 MIN CLKR/X ext CLKR/X ext CLKR/X ext CLKR/X ext, MCBSP2.FS R/X ext CLKR/X ext CLKR/X ext CLKR/X ext, MCBSP2.FS R/X ext CLKR/X ext CLKX int CLKX ext CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext CLKR int CLKR ext CLKX int CLKX ext 25 31 25 7 24 15 3 16 3 3 13 13 21 3 22 3 19 10 2P 0.45P MAX UNIT ns ns 12 12 6 12 12 6 ns ns ns ns ns Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Regardless of whether MCBSP.CLKS is internally or externally clocked, P = 1/(DSPXOR_CK) for McBSP1 and McBSP3, and P= 1/(AMPER_CK) for McBSP2. See the OMAP5910 Dual-Core Processor Clock Generation and System Reset Management Reference Guide (literature number SPRU678) for additional details. For McBSP1 and McBSP2, the receiver clock and frame sync inputs are driven by FSX and CLKX via internal loopback connections enabled via software configuration. August 2002 - Revised August 2004 SPRS197D 141 Electrical Specifications Table 5-14. McBSP Timing Requirements (Continued) NO. McBSP1 M18 th(CKRL-DRV) Hold time DR valid after CLKR/X low time, McBSP2 McBSP3 McBSP1 M19 tsu(FXH-CKXL) Setup time external FSX high before CLKX low time, McBSP2 McBSP3 McBSP1 M20 th(CKXL-FXH) Hold time external FSX high after CLKX low time, McBSP2 McBSP3 MIN CLKX int 3 3 3 3 3 3 30 25 28 27 28 27 3 10 3 3 3 3 CLKX ext CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext MAX UNIT ns ns ns Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Regardless of whether MCBSP.CLKS is internally or externally clocked, P = 1/(DSPXOR_CK) for McBSP1 and McBSP3, and P= 1/(AMPER_CK) for McBSP2. See the OMAP5910 Dual-Core Processor Clock Generation and System Reset Management Reference Guide (literature number SPRU678) for additional details. For McBSP1 and McBSP2, the receiver clock and frame sync inputs are driven by FSX and CLKX via internal loopback connections enabled via software configuration. 142 SPRS197D August 2002 - Revised August 2004 Electrical Specifications Table 5-15. McBSP Switching Characteristics NO. M0 M1 M2 M3 M4 td(CKSH-CKRXH) tc(CKRX) tw(CKRXH) tw(CKRXL) td(CKRH-FRV) PARAMETER Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input Cycle time, CLKR/X Pulse duration, CLKR/X high Pulse duration, CLKR/X low Delay time CLKR high to internal FSR valid time, McBSP2 McBSP1 M5 td(CKXH-FXV) Delay time CLKX high to internal FSX valid time, McBSP2 McBSP3 McBSP1 M7 td(CKXH-DXV) Delay time, CLKX high to DX valid. This applies to all bits except the first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode. McBSP2 McBSP3 McBSP1 Delay time, FSX high to DX valid M9 td(FXH-DXV) Only O l applies to first bit transmitted when in Data li fi bi i dh iD Delay 0 (XDATDLY=00b) mode mode. McBSP2 McBSP3 MIN McBSP1 CLKR/X int CLKR/X int CLKR/X int CLKR/X int CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext FSX int FSX ext FSX int FSX ext FSX int FSX ext 2 2P 0.45D 0.45C -1 -3 -4 7 -1 2 -1 2 -2 7 0 3 -1 1 MAX 33 UNIT ns ns 0.55D 0.55C 13 24 13 39 4 24 9 37 7 40 10 27 10 16 28 25 30 27 10 27 ns ns ns ns ns ns ns Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz. T=CLKRX period = (1 + CLKGDV) * P C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even Only DXENA=0 is supported for all OMAP5910 McBSPs. August 2002 - Revised August 2004 SPRS197D 143 Electrical Specifications MCBSP1.CLKS M0 M1, M11 M2, M12 M3, M12 CBSPx.CLKR/X M4 CBSP2.FSR (int) M13 MCBSPx.FSR/X (ext) M14 M4 M14 M13 M15 M17 M16 M18 Bit (n-1) M17 (n-2) M18 Bit (n-1) M17 Bit (n-1) (n-2) M18 (n-2) (n-3) (n-3) (n-4) MCBSPx.DR (RDATDLY=00b) MCBSPx.DR (RDATDLY=01b) MCBSPx.DR (RDATDLY=10b) For McBSP1 and McBSP3, the receiver clock and frame sync inputs are driven by FSX and CLKX via internal loopback connections enabled via software configuration. The M13 and M14 descriptors are applicable only to McBSP2. Figure 5-18. McBSP Receive Timings M1, M11 M2, M12 M3, M12 MCBSPx.CLKX M5 MCBSPx.FSX (int) M19 MCBSPx.FSX (ext) MCBSPx.DX (XDATDLY=00b) Bit 0 M20 M9 Bit (n-1) (n-2) M7 MCBSPx.DX (XDATDLY=01b) Bit 0 Bit (n-1) M7 M5 M13 M14 M7 (n-3) (n-4) (n-2) M7 (n-3) MCBSPx.DX (XDATDLY=10b) Bit 0 Bit (n-1) (n-2) Figure 5-19. McBSP Transmit Timings 144 SPRS197D August 2002 - Revised August 2004 Electrical Specifications 5.9.2 McBSP as SPI Master or Slave Timing Table 5-16 to Table 5-23 assume testing over recommended operating conditions (see Figure 5-20 through Figure 5-23). Table 5-16. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) NO. NO M30 M31 M32 M33 MASTER MIN tsu(DRV-CKXL) th(CKXL-DRV) tsu(BFXL-CKXH) su(BFXL CKXH) tc(CKX) Setup time, MCBSPx.DR valid before MCBSPx.CLKX low Hold time, MCBSPx.DR valid after MCBSPx.CLKX low McBSP1 Setup ti S t time, MCBSPx.FSX low before MCBSP FSX l bf MCBSPx.CLKX high Cycle time, MCBSPx.CLKX McBSP2 McBSP3 2P 15 2 MAX SLAVE MIN 2 - 6P 6 + 6P 21 5 10 16P MAX UNIT ns ns ns ns For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1. P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz. Table 5-17. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) NO. NO M24 M25 M26 M29 PARAMETER th(CKXL-FXL) td(FXL-CKXH) td(CKXH-DXV) td(FXL-DXV) Hold time, MCBSPx.FSX low after MCBSPx.CLKX low Delay time, MCBSPx.FSX low to MCBSPx.CLKX high# Delay time, MCBSPx.CLKX high to MCBSPx.DX valid Delay time, MCBSPx.FSX low to MCBSPx.DX valid MASTER MIN 0.45T 0.45C -1 MAX 0.55T 0.55C 7 SLAVE MIN MAX UNIT ns ns 3P + 2 5P+ 18 4P + 18 ns ns For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1. P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz. T = CLKX period = (1 + CLKGDV) * P C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even FSRP = FSXP = 1. As a SPI master, MCBSPx.FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on MCBSPx.FSX and MCBSPx.FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # MCBSPx.FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (MCBSPx.CLKX). M33 LSB CLKX M24 FSX M32 MSB M25 M29 M26 DX Bit 0 M30 DR Bit 0 Bit(n-1) Bit(n-1) (n-2) M31 (n-2) (n-3) (n-4) (n-3) (n-4) Figure 5-20. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 August 2002 - Revised August 2004 SPRS197D 145 Electrical Specifications Table 5-18. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) NO. NO M39 M40 M41 M42 MASTER MIN tsu(DRV-CKXH) th(CKXH-DRV) tsu(FXL-CKXH) su(FXL CKXH) tc(CKX) Setup time, MCBSPx.DR valid before MCBSPx.CLKX high Hold time, MCBSPx.DR valid after MCBSPx.CLKX high McBSP1 Setup ti S t time, MCBSPx.FSX low before MCBSP FSX l bf MCBSPx.CLKX high Cycle time, MCBSPx.CLKX McBSP2 McBSP3 2P 15 2 MAX SLAVE MIN 2 - 6P 6 +6P 21 5 10 16P MAX UNIT ns ns ns ns For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1. P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz. Table 5-19. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) NO. NO M34 M35 M36 M38 PARAMETER th(CKXL-FXL) td(FXL-CKXH) td(CKXL-DXV) td(FXL-DXV) Hold time, MCBSPx.FSX low after MCBSPx.CLKX low Delay time, MCBSPx.FSX low to MCBSPx.CLKX high# Delay time, MCBSPx.CLKX low to MCBSPx.DX valid Delay time, MCBSPx.FSX low to MCBSPx.DX valid MASTER MIN 0.45C 0.45T -1 MAX 0.55C 0.55T 7 D +20 SLAVE MIN MAX UNIT ns ns 3P + 2 5P + 18 4P + 18 ns ns For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1. P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz. T = CLKX period = (1 + CLKGDV) * P C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even FSRP = FSXP = 1. As a SPI master, MCBSPx.FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on MCBSPx.FSX and MCBSPx.FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # MCBSPx.FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (MCBSPx.CLKX). LSB MCBSPx.CLKX M34 MCBSPx.FSX M38 MCBSPx.DX Bit 0 M39 MCBSPx.DR Bit 0 Bit(n-1) Bit(n-1) M36 (n-2) M40 (n-2) (n-3) (n-4) (n-3) (n-4) M35 M41 MSB M42 Figure 5-21. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 146 SPRS197D August 2002 - Revised August 2004 Electrical Specifications Table 5-20. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) NO. NO M49 M50 M51 M52 MIN tsu(DRV-CKXH) th(CKXH-DRV) tsu(FXL-CKXL) su(FXL CKXL) tc(CKX) Setup time, MCBSPx.DR valid before MCBSPx.CLKX high Hold time, MCBSPx.DR valid after MCBSPx.CLKX high McBSP1 Setup ti S t time, MCBSPx.FSX low before MCBSP FSX l bf MCBSPx.CLKX low Cycle time, MCBSPx.CLKX McBSP2 McBSP3 MASTER MIN 15 2 MAX SLAVE MIN 2 - 2P 6 + 6P 21 5 10 MAX UNIT ns ns ns ns 2P 16P For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz. Table 5-21. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) NO. NO M43 M44 M45 M48 PARAMETER th(CKXH-FXL) td(FXL-CKXL) td(CKXL-DXV) td(FXL-DXV) Hold time, MCBSPx.FSX low after MCBSPx.CLKX high Delay time, MCBSPx.FSX low to MCBSPx.CLKX low# Delay time, MCBSPx.CLKX low to MCBSPx.DX valid Delay time, MCBSPx.FSX low to MCBSPx.DX valid MASTER MIN 0.45T 0.45D -1 MAX 0.55T 0.55D 7 SLAVE MIN MAX UNIT ns ns 3P + 2 5P + 18 4P + 18 ns ns For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1. P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz. T = CLKX period = (1 + CLKGDV) * P D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even FSRP = FSXP = 1. As a SPI master, MCBSPx.FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on MCBSPx.FSX and MCBSPx.FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # MCBSPx.FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (MCBSPx.CLKX). LSB MCBSPx.CLKX M43 MCBSPx.FSX M48 M45 MCBSPx.DX Bit 0 M49 MCBSPx.DR Bit 0 Bit(n-1) Bit(n-1) (n-2) M50 (n-2) (n-3) (n-4) (n-3) (n-4) M44 M51 MSB M52 Figure 5-22. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 August 2002 - Revised August 2004 SPRS197D 147 Electrical Specifications Table 5-22. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) NO. NO M58 M59 M60 M61 MIN tsu(DRV-CKXL) th(CKXL-DRV) tsu(FXL-CKXL) su(FXL CKXL) tc(CKX) Setup time, MCBSPx.DR valid before MCBSPx.CLKX low Hold time, MCBSPx.DR valid after MCBSPx.CLKX low McBSP1 Setup ti S t time, MCBSPx.FSX low before MCBSP FSX l bf MCBSPx.CLKX low Cycle time, MCBSPx.CLKX McBSP2 McBSP3 MASTER MIN 15 2 MAX SLAVE MIN 2 - 6P 6 + 6P 21 5 10 MAX UNIT ns ns ns ns 2P 16P For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1. P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz. Table 5-23. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) NO. NO M53 M54 M55 M57 PARAMETER th(CKXH-FXL) td(FXL-CKXL) td(CKXH-DXV) td(FXL-DXV) Hold time, MCBSPx.FSX low after MCBSPx.CLKX high Delay time, MCBSPx.FSX low to MCBSPx.CLKX low# Delay time, MCBSPx.CLKX high to MCBSPx.DX valid Delay time, MCBSPx.FSX low to MCBSPx.DX valid MASTER MIN 0.45D 0.45T -1 MAX 0.55D 0.55T 7 C + 20 SLAVE MIN MAX UNIT ns ns 3P + 2 5P + 18 4P + 18 ns ns For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1. P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz. T = CLKX period = (1 + CLKGDV) * P C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even FSRP = FSXP = 1. As a SPI master, MCBSPx.FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on MCBSPx.FSX and MCBSPx.FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # MCBSPx.FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (MCBSPx.CLKX). M60 MSB M61 MCBSPx.CLKX LSB M53 M54 MCBSPx.FSX M57 MCBSPx.DX Bit 0 M58 MCBSPx.DR Bit 0 Bit(n-1) Bit(n-1) M55 (n-2) M59 (n-2) (n-3) (n-4) (n-3) (n-4) Figure 5-23. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 148 SPRS197D August 2002 - Revised August 2004 Electrical Specifications 5.10 Multichannel Serial Interface (MCSI) Table 5-24 and Table 5-25 assume testing over recommended operating conditions (see Figure 5-24 and Figure 5-25). Table 5-24. MCSI Timing Requirements NO. MC11 MC12 MC13 MC14 MC15 MC16 MC17 MC18 MC19 MIN fop(CLK) tw(CLKH) tw(CLKL) tr(CLK) tf(CLK) tsu(FSH-CLKL) th(CLKL-FSH) tsu(DIV-CLKL) th(CLKL-DIV) Operating frequency, MCSIx.CLK Pulse duration, MCSIx.CLK high Pulse duration, MCSIx.CLK low Rise time, MCSIx.CLK Fall time, MCSIx.CLK Hold time, external MCSIx.SYNC high after MCSIx.CLK low time MCSIx SYNC MCSIx CLK Setup time MCSIx DIN valid before MCSIx CLK low time, MCSIx.DIN MCSIx.CLK Hold time MCSIx DIN valid after MCSIx CLK low time, MCSIx.DIN MCSIx.CLK Slave Slave Slave Slave Slave 18 6 27 18 0 6 Slave Master Slave Master Slave 0.45P MAX B UNIT MHz ns ns ns ns ns ns ns ns 0.45P 0.55P 0.55P 12 12 Setup time, external MCSIx.SYNC high before MCSIx CLK low Slave time MCSIx SYNC MCSIx.CLK P = MCSIx.CLK period [tc(CLK)] in nanoseconds. B = Base frequency for OMAP5910 (12 or 13 MHz). Table 5-25. MCSI Switching Characteristics NO. MC1 MC2 MC3 MC4 MC7 MC8 PARAMETER fop(CLK) tw(CLKH) tw(CLKL) td(CLKH-FS) td(CLKH-DOV) ten(CLKH-DO) Operating frequency, MCSIx.CLK Pulse duration, MCSIx.CLK high Pulse duration, MCSIx.CLK low Delay time MCSIx CLK high to MCSIx SYNC transition time, MCSIx.CLK MCSIx.SYNC Delay time MCSIx CLK high to MCSIx DOUT valid time, MCSIx.CLK MCSIx.DOUT Enable time MCSIx DOUT driven from MCSIx CLK high time, MCSIx.DOUT MCSIx.CLK Master Master Master Master Master Slave Master Slave MIN 0.45P 0.45P 0 0 2 0 2 MAX 0.5B 0.55P 0.55P 5 5 30 UNIT MHz ns ns ns ns ns P = MCSIx.CLK period [tc(CLK)] in nanoseconds. B = Base frequency for OMAP5910 (12 or 13 MHz). August 2002 - Revised August 2004 SPRS197D 149 Electrical Specifications 1/MC1 MC2 MC3 MCSIx.CLK MC4 MCSIx.SYNC (normal short) MCSIx.SYNC (alt. short) MCSIx.SYNC (normal long) MCSIx.SYNC (alt. long) MC8 MCSIx.DOUT MC18 MCSIx.DIN Bit (n) MC18 Bit (n) MC19 (n-1) MC19 (0) MC7 (n-1) (0) MC4 MC4 MC4 MC4 MC4 MC4 MC4 Figure 5-24. MCSI Master Mode Timings 1/MC11 MC12 MC13 MCSIx.CLK MCSIx.SYNC (normal short) MCSIx.SYNC (alt. short) MCSIx.SYNC (normal long) MCSIx.SYNC (alt. long) MC8 MCSIx.DOUT MC18 MCSIx.DIN Bit (n) MC18 MC7 Bit (n) MC19 (n-1) MC19 (0) (n-1) (0) MC16 MC16 MC16 MC17 MC15 MC14 MC16 MC17 MC17 M17 Figure 5-25. MCSI Slave Mode Timings 150 SPRS197D August 2002 - Revised August 2004 Electrical Specifications 5.11 Camera Interface Timings Table 5-26 assumes testing over recommended operating conditions (see Figure 5-26). Table 5-26. Camera Interface Timing Requirements NO. C1 C2 C3 C5 C6 C7 C8 MIN 1 / [ tc(LCKH-HSV) ] 1 / [ tc(XCKH-HSV) ] tw(LCK) tsu(LCKH-DV) th(DV-LCKH) tsu(LCKH-DV) th(DV-CLKH) Operating frequency, CAM.LCLK Operating frequency, CAM.EXCLK Pulse duration, CAM.LCLK high or low Setup time, CAM.D[7:0] data valid before CAM.LCLK high Hold time, CAM.D[7:0] data valid after CAM.LCLK high Setup time, CAM.VS/CAM.HS active before CAM.LCLK high Hold time, CAM.VS/CAM.HS active after CAM.LCLK high 0.45P 1 9 MAX 13 24 0.55P UNIT MHz MHz ns ns ns ns ns 1 9 P = period of CAM.LCLK in nanoseconds (ns). Polarity of CAM.LCLK is selectable via the POLCLK bit in the CTRLCLOCK register. Although data is latched on rising CAM.LCLK in the timing diagrams, these timing parameters also apply to falling CAM.LCLK when POLCLK = 1. C3 CAM.LCLK C7 CAM.VS C1 C3 C8 C7 CAM.HS C5 CAM.D[7:0] U1 Y1 C6 C5 V1 C8 C6 Yn Figure 5-26. Camera Interface Timings August 2002 - Revised August 2004 SPRS197D 151 Electrical Specifications 5.12 LCD Controller Timings Table 5-27 assumes testing over recommended operating conditions (see Figure 5-27 and Figure 5-28). Table 5-27. LCD Controller Switching Characteristics NO. L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 PARAMETER td(CLKH-HSV) td(CLKL-HSV) td(CLKH-VSV) td(CLKL-VSV) td(CLKH-PV) td(CLKH-PIV) td(CLKL-PV) td(CLKL-PIV) td(CLKL-ACV) td(CLKL-ACV) Delay time, LCD.PCLK high to LCD.HS transition Delay time, LCD.PCLK low to LCD.HS transition Delay time, LCD.PCLK high to LCD.VS transition Delay time, LCD.PCLK low to LCD.VS transition Delay time, LCD.PCLK high to pixel data valid (LCD.P[15:0]) Delay time, LCD.PCLK high to pixel data invalid (LCD.P[15:0]) Delay time, LCD.PCLK low to pixel data valid (LCD.P[15:0]) Delay time, LCD.PCLK low to pixel data invalid (LCD.P[15:0]) Delay time, LCD.PCLK high to LCD.AC transition Delay time, LCD.PCLK low to LCD.AC transition MIN 1 1 1 1 1 MAX 11 11 11 11 11 11 UNIT ns ns ns ns ns ns ns ns ns ns 1 1 1 5+P 5+P Although timing diagrams illustrate the logical function of the TFT mode, static timings apply to all supported modes of operation. Likewise, LCD.HS, LCD.VS, and LCD.AC are shown as active-low, but each may optionally be configured as active-high. P = period of internal undivided pixel clock HSW LCD.PCLK VSW VFP HFP PPL HBP L4 LCD.VS L2 LCD.HS L4 L2 L5 LCD.P[15:0] L9 LCD.AC L6 D2 D3 Dn L9 D1 Delays for HSW (LCD.HS Width), VSW (LCD.VS Width), VFP (Vertical Front Porch), HFP (Horizontal Front Porch), HBP (Horizontal Back Porch) and PPL (Pixels per Line) are programmable in number of LCD.PCLK cycles via the LCD configuration registers. Figure 5-27. TFT Mode (LCD.HS/LCD.VS on Falling and LCD.Px on Rising LCD.PCLK) 152 SPRS197D August 2002 - Revised August 2004 Electrical Specifications VSW HFP HBP HSW LCD.PCLK VFP PPL L3 LCD.VS L1 LCD.HS L1 L3 L7 LCD.P[15:0] L10 LCD.AC L8 D2 D3 Dn L10 D1 Delays for HSW (LCD.HS Width), VSW (LCD.VS Width), VFP (Vertical Front Porch), HFP (Horizontal Front Porch), HBP (Horizontal Back Porch) and PPL (Pixels per Line) are programmable in number of LCD.PCLK cycles via the LCD configuration registers. Figure 5-28. TFT Mode (LCD.HS/LCD.VS on Rising and LCD.Px on Falling LCD.PCLK) August 2002 - Revised August 2004 SPRS197D 153 Electrical Specifications 5.13 Multimedia Card/Secure Digital (MMC/SD) Timings Table 5-28 and Table 5-29 assume testing over recommended operating conditions (see Figure 5-29 through Figure 5-32). Table 5-28. MMC/SD Timing Requirements NO. M1 M2 M3 M4 tsu(CMDV-CLKH) th(CLKH-CMDV) tsu(DATV-CLKH) th(CLKH-DATV) Setup time, MMC.CMD valid before MMC.CLK high Hold time, MMC.CMD invalid after MMC.CLK high Setup time, MMC.DATx valid before MMC.CLK high Hold time, MMC.DATx invalid after MMC.CLK high MIN 12 2 12 2 MAX UNIT ns ns ns ns Table 5-29. MMC/SD Switching Characteristics NO. M7 M8 M9 M10 M11 PARAMETER tc(CLK) tw(CLKH) tw(CLKL) td(CLKH-CMD) td(CLKH-DAT) Cycle time, MMC CLK time MMC.CLK Pulse Duration, MMC.CLK high Pulse Duration, MMC.CLK low Delay time, MMC.CLK high to MMC.CMD transition Delay time, MMC.CLK high to MMC.DATx transition MIN 41.7 MAX 5.31 UNIT ns us ns ns 20 20 4 4 48 48 ns ns MMC.CLK period and pulse duration depends upon software configuration. M7 MMC.CLK M10 MMC.CMD M8 M9 M10 Start XMIT Valid Valid M10 Valid End M10 Figure 5-29. MMC/SD Host Command Timings M7 MMC.CLK M1 M2 MMC.CMD Start XMIT Valid Valid Valid End M8 M9 M1 M2 Figure 5-30. MMC/SD Card Response Timings 154 SPRS197D August 2002 - Revised August 2004 Electrical Specifications M7 MMC.CLK M11 M11 MMC.DATx Start D0 D1 D2 M11 Dx M8 M9 M11 End Figure 5-31. MMC/SD Host Write Timings M7 MMC.CLK M3 M8 M9 M3 M4 Start D0 D1 D2 Dx End M4 MMC.DATx Figure 5-32. MMC/SD Host Read and Card CRC Status Timings August 2002 - Revised August 2004 SPRS197D 155 Electrical Specifications 5.14 I2C Timings Table 5-30 assumes testing over recommended operating conditions (see Figure 5-33). Table 5-30. I2C Signals (I2C.SDA and I2C.SCL) Switching Characteristics NO. IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 IC10 IC11 IC12 IC13 IC14 IC15 PARAMETER tc(SCL) tsu(SCLH-SDAL) th(SCLL-SDAL) tw(SCLL) tw(SCLH) tsu(SDA-SDLH) th(SDA-SDLL) tw(SDAH) tr(SDA) tr(SCL) tf(SDA) tf(SCL) tsu(SCLH-SDAH) tw(SP) Cb Cycle time, I2C.SCL Setup time, I2C.SCL high before I2C.SDA low (for a repeated START condition) Hold time, I2C.SCL low after I2C.SDA low (for a repeated START condition) Pulse duration, I2C.SCL low Pulse duration, I2C.SCL high Setup time, I2C.SDA valid before I2C.SCL high Hold time, I2C.SDA valid after I2C.SCL low (for I2C bus devices) Pulse duration, I2C.SDA high between STOP and START conditions Rise time, I2C.SDA Rise time, I2C.SCL Fall time, I2C.SDA Fall time, I2C.SCL Setup time, I2C.SCL high before I2C.SDA high (for STOP condition) Pulse duration, spike (must be suppressed) Capacitive load for each bus line STANDARD MODE MIN 10 4.7 4 4.7 4 250 0 4.7 1000 1000 300 300 4.0 400 FAST MODE MIN 2.5 0.6 0.6 1.3 0.6 100 0 1.3 300 300 300 300 0.6 0 50 400 0.9 MAX UNIT s s s s s ns s s ns ns s ns pF MAX In the master-only I2C operating mode of OMAP5910, minimum cycle time for I2C.SCL is 12 s. The maximum th(SCLL-SDAL) has only to be met if the device does not stretch the low period (tw(SCLL)) of the I2C.SCL signal. C = The total capacitance of one bus line in pF. b I2C.SDA IC8 IC4 IC10 I2C.SCL IC1 IC7 IC3 Stop Start Repeated Start IC12 IC3 IC2 Stop IC5 IC6 IC14 IC13 NOTES: A. A device must internally provide a hold time of at least 300 ns for the I2C.SDA signal (referred to the VIHmin of the I2C.SCL signal) to bridge the undefined region of the falling edge of I2C.SCL. B. The maximum th(SCLL-SDAL) has only to be met if the device does not stretch the LOW period (tw(SCLL)) of the I2C.SCL signal. C. A Fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SDLH) * 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the I2C.SCL signal. If such a device does stretch the LOW period of the I2C.SCL signal, it must output the next data bit to the I2C.SDA line tr max + tsu(SDA-SDLH) = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the I2C.SCL line is released. D. Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall times are allowed. Figure 5-33. I2C Timings 156 SPRS197D August 2002 - Revised August 2004 Electrical Specifications 5.15 Universal Serial Bus (USB) Timings All OMAP5910 USB interfaces are compliant with the Universal Serial Bus Specification, Revision 2.0. Table 5-31 assumes testing over recommended operating conditions (see Figure 5-34). Table 5-31. USB Integrated Transceiver Interface Switching Characteristics NO. U1 U2 U3 U4 U5 U6 PARAMETER tr tf tRFM VCRS tjr fop Rise time, USB.DP and USB.DM signals Fall time, USB.DP and USB.DM signals Rise/Fall time matching Output signal cross-over voltage Differential propagation jitter Operating frequency LOW SPEED 1.5 Mbps MIN 75 75 80 1.3 -25 MAX 300 300 125 2.0 25 1.5 FULL SPEED 12 Mbps MIN 4 4 90 1.3 -2 MAX 20 20 111.11 2.0 2 12 UNIT ns ns % V ns MHz Low Speed: CL = 200 pF, Full Speed: CL = 50 pF t RFM = (tr/tf) x 100 t jr = tpx(1) - tpx(0) f op = 1/tper REF clock USB.DM VCRS USB.DP tpx(0) VOH VOL tper - tjr 90% 10% U1 U2 tpx(1) "REF clock" is not an actual device signal, but an ideal reference clock against which relative timings are specified. REF clock is assumed to be 12 MHz for full-speed mode or 1.5 MHz for low-speed mode). Figure 5-34. USB Integrated Transceiver Interface Timings August 2002 - Revised August 2004 SPRS197D 157 Electrical Specifications 5.16 MICROWIRE Interface Timings Table 5-32 and Table 5-33 assume testing over recommended operating conditions (see Figure 5-35). Table 5-32. MICROWIRE Timing Requirements NO. W5 W6 MIN tsu(SDI-SCLK) th(SCLK-SDI) Setup time, UWIRE.SDI valid before UWIRE.SCLK active edge Hold time, UWIRE.SDI invalid after UWIRE.SCLK active edge 21 6 MAX UNIT ns ns Polarity of UWIRE.SCLK and the active clock edge (rising or falling) on which SDO data is driven and SDI data is latched is all software configurable. These timings apply to all configurations regardless of UWIRE.SCLK polarity and which clock edges are used to drive output data and capture input data. Table 5-33. MICROWIRE Switching Characteristics NO. W1 W2 W3 W4 PARAMETER fop(SCLK) tw(SCLK) td(SCLK-SDO) td(CS-SCLK) Operating Frequency, UWIRE.SCLK Pulse Duration, UWIRE.SCLK high/low Delay time, UWIRE.SCLK active edge to UWIRE.SDO transition Delay time, UWIRE.CSx active to UWIRE.SCLK active MIN 0.45P -3 1.5P MAX 3 0.55P 6 UNIT MHz ns ns ns Polarity of UWIRE.SCLK and the active clock edge (rising or falling) on which SDO data is driven and SDI data is latched is all software configurable. These timings apply to all configurations regardless of UWIRE.SCLK polarity and which clock edges are used to drive output data and capture input data. P = UWIRE.SCLK cycle time in ns. UWIRE.CSx W4 UWIRE.SCLK W3 Valid Valid Valid W5 UWIRE.SDI Valid W6 Valid Valid W2 W2 [1/W1] W4 W3 UWIRE.SDO NOTE: The polarities of UWIRE.CSx and UWIRE.SCLK and the active UWIRE.SCLK edges on which SDO is driven and SDI is sampled are all software configurable. Figure 5-35. MICROWIRE Timings 158 SPRS197D August 2002 - Revised August 2004 Electrical Specifications 5.17 HDQ/1-Wire Interface Timings Table 5-34 and Table 5-35 assume testing over recommended operating conditions (see Figure 5-36 through Figure 5-39). Table 5-34. HDQ/1-Wire Timing Requirements MIN H1 H2 H3 tc tv tv Cycle time, master read Read one data valid after HDQ low Read zero data hold after HDQ low OMAP5910 base frequency = 12 MHz OMAP5910 base frequency = 13 MHz 190 32 80 190 190 190 12 1 13.6 MAX 250 50 145 320 303 UNIT s s s s s s s s H4 tv tc tv tdis Response time from HDQ slave device W1 W2 W3 Cycle time, master read Read data valid after HDQ low (master sample window) Recovery time after slave device inactive HDQ timing is OMAP5910 default. 1-Wire timing is selectable through software. Table 5-35. HDQ/1-Wire Switching Characteristics PARAMETER H5 H6 tc td Cycle time, master write Write one data valid after HDQ low OMAP5910 base frequency = 12 MHz OMAP5910 base frequency = 13 MHz MIN 190 32 100 92 190 40 190 15 1.1 1 90 1.4 50 145 145 MAX UNIT s s s s s s s s s s H7 td tw tw tc td td tdis Write zero data hold after HDQ low H8 H9 W4 W5 W6 W7 Pulse width, HDQ low for break pulse (reset) Pulse width, HDQ high for break pulse recovery Cycle time, master write Write zero master inactive after HDQ low Write one master inactive after HDQ low Recovery time after master inactive August 2002 - Revised August 2004 SPRS197D 159 Electrical Specifications Read 1 HDQ H2 H3 H1 Read 0 Figure 5-36. OMAP5910 HDQ Interface Reading From HDQ Slave Device Write 1 HDQ H6 H7 H5 Write 0 Figure 5-37. OMAP5910 HDQ Interface Writing to HDQ Slave Device Break Command Byte (Written by OMAP5910) Register Address 1 6 7 (MSB) 0 (LSB) Data Byte (Received by OMAP5910 from Slave) 1 6 7 (MSB) 0 (LSB) HDQ H4 Figure 5-38. Typical Communication Between OMAP5910 HDQ and HDQ Slave HDQ H12 H9 H11 H8 Figure 5-39. HDQ/1-Wire Break (Reset) Timing 160 SPRS197D August 2002 - Revised August 2004 Glossary 6 Glossary DEFINITION a serial protocol defined by Dallas Semiconductor Corporation Advanced Audio Coding (standard) (ISO/IEC 13818-7) Interface Standard for Codecs arithmetic/logic unit Adaptive Multi-Rate asynchronous static RAM address unit binary coded decimal ball grid array complementary metal oxide semiconductor coprocessor 15 cyclic redundancy check Chip Support Library clear-to-send dual-access RAM discrete cosine transform direct memory access digital phase-locked loop digital signal processor DSP Library data-set-ready data-terminal-ready data unit external memory interface fast external memory interface slow endpoint electrostatic discharge frame adjustment counter Fast Fourier Transform first-in first out fast interrupt request General Packet Radio Service Global System for Mobile Communications an ITU-TSS standard Human Body Model Horizontal Back Porch ACRONYM 1-wire AAC AC97 ALU AMR ASRAM AU BCD BGA CMOS CP15 CRC CSL CTS DARAM DCT DMA DPLL DSP DSPLIB DSR DTR DU EMIFF EMIFS EP ESD ETM FAC FFT FIFO FIQ GPRS GSM H.26x HBM HBP August 2002 - Revised August 2004 SPRS197D 161 Glossary ACRONYM HDQ HFP HOM HS I-cache I2C I2S iDCT I/F IFR IMGLIB IMIF IMR IOM-2 IrDA IRQ IU JPEG LB LCD LPG LSB LVCMOS MAC MCSI McBSP MMC MMC/SD MMU MPEG MPU MPUI MPUIO MSB MVIP ODM OEM OHCI OS DEFINITION a single-wire serial interface protocol defined by Benchmarq Controls Inc. Horizontal Front Porch host-only mode high-speed instruction cache Inter-integrated circuit Inter-IC Sound (specification) Inverse Discrete Cosine Transform interface Interrupt Flag Register Image/Video Processing Library internal memory interface Interrupt Mask Register ISDN Oriented Modular Interface Revision 2 infrared data adapter low-priority interrupt request instruction unit Joint Photographic Experts Group - standard for compressed still-picture data local bus liquid crystal display LED pulse generator least significant bit low-voltage CMOS multiply-accumulate multichannel serial interface multichannel buffered serial port multimedia card multimedia card/secure digital memory management unit Moving Picture Experts Group - proposed standard for compressed video data microprocessor unit microprocessor unit interface microprocessor unit I/O most significant bit multi-vendor integration protocol original design manufacturer original equipment manufacturer Open Host Controller Interface operating system Benchmarq is a trademark of Texas Instruments. 162 SPRS197D August 2002 - Revised August 2004 Glossary ACRONYM PPL PU PWL PWT RISC RTC RTS SAM SARAM SD SDRAM SDW SIR SPI SRAM SRG STN T1/E1 DEFINITION pixels per line program unit pulse-width light pulse-width tone reduced instruction set computer real-time clock request-to-send shared-access mode single-access RAM secure digital synchronous dynamic RAM short distance wireless slow infrared serial peripheral interface static RAM Sample Rate Generator super twisted nematic T1 is a digital transmission link with a capacity of 1.544 Mbps. It uses two pairs of normal twisted-wires and can handle 24-voice conversations, each digitized using mu-law coding at 64 kbps. T1 is used in USA, Canada, Hong Kong, and Japan. E1 is a digital transmission link with a capacity of 2.048 Mbps. It is the European equivalent of T1. It can handle 30-voice conversations, each digitized using A-law coding at 64 kbps. test access port traffic controller thin-film transistor Texas Instruments TI peripheral bus Translation Look-Aside Buffer Translation Table Base universal asynchronous receiver/transmitter ultra low-power device uniform resource locator universal serial bus Universal Serial Bus Specification Revision 2.0 Vertical Front Porch virtual index virtual tag write buffer watchdog timer Windows Media Audio Windows Media Video TAP TC TFT TI TIPB TLB TTB UART ULPD URL USB USB2.0 VFP VIVT WB WDT WMA WMV August 2002 - Revised August 2004 SPRS197D 163 Mechanical Data 7 Mechanical Data The following mechanical package diagram(s) reflect the most current released mechanical data available for the designated device(s). 164 SPRS197D August 2002 - Revised August 2004 PACKAGE OPTION ADDENDUM www.ti.com 20-Dec-2004 PACKAGING INFORMATION Orderable Device OMAP5910GGZG2 OMAP5910JGDY2 OMAP5910JGZG2 OMAP5910JZZG2 Status (1) OBSOLETE ACTIVE ACTIVE ACTIVE Package Type BGA BGA BGA BGA MI CROSTA R BGA BGA BGA Package Drawing GZG GDY GZG ZZG Pins Package Eco Plan (2) Qty 289 289 289 289 84 160 160 None None None Green (RoHS & no Sb/Br) None None None Lead/Ball Finish Call TI SNPB SNPB SNAGCU MSL Peak Temp (3) Call TI Level-3-220C-168HR Level-4-220C-72HR Level-4-260C-72HR POMAP5910GGDY2 POMAP5910GGZG2 POMAP5910JGDY2 (1) OBSOLETE OBSOLETE OBSOLETE GDY GZG GDY 289 289 289 Call TI Call TI Call TI Call TI Call TI Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPBG179A - FEBRUARY 2001 - REVISED JANUARY 2002 GZG (S-PBGA-N289) PLASTIC BALL GRID ARRAY 12,10 SQ 11,90 0,50 10,00 TYP Y V T P M K H F D B AA W U R N L J G E C A 1 2 3 4 5 6 7 9 11 13 15 17 19 21 8 10 12 14 16 18 20 Bottom View 0,50 Seating Plane 0,08 4173512-6/D 11/01 A1 Corner 0,95 0,85 1,20 MAX 0,35 0,25 0,05 M 0,30 0,20 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGA configuration MicroStar BGA is a trademark of Texas Instruments. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 This datasheet has been download from: www..com Datasheets for electronics components. |
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